6.7. Altera Devices
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## 6.7. Altera Devices

The Debug Sprite can be used to debug applications running on a Cortex-M1 core embedded in an Altera FPGA supporting the System-Level Debug (SLD) architecture. Currently, the Sprite supports the Cyclone III FPGA Starter board on Microsoft Windows hosts.

The Debug Sprite accepts two forms of the `device-url` for Altera devices. For the common case where you have only one Altera Cortex-M1 device configured, you can use simply:

    altera://

The full form of the `device-url` is:

    altera://usbX/hubY/nodeZ

where `X`, `Y`, and `Z` are non-negative integers. The SLD architecture forms a hierarchy; there may be multiple USB Blaster devices (numbered by `X`), multiple Altera FPGAs (numbered by `Y`) per USB Blaster, and multiple nodes (numbered by `Z`) per FPGA.

The Debug Sprite can autodetect connected Altera Cortex-M1 devices. Invoking the Sprite with the `-i` option, as described in Section 6.1, “Probing for Debug Devices”, displays the `device-url` for each detected device:

    > arm-none-eabi-sprite -i
    ...
    altera: Altera SLD Hub
      altera://usb0/hub0/node1 - Altera Cortex-M Device

### 6.7.1. Setting Up the Altera Device

Follow these steps for initial installation and set up of the Altera device.

1. Install Quartus II Web Edition (or any equivalent), available from Altera.

2. Install drivers for USB Blaster, also available from Altera.

3. Install Sourcery CodeBench Lite for ARM EABI. See Chapter 2, “Installation and Configuration”.

4. Connect the board and the host computer with a USB cable.

5. Turn on the board.

6. Use Quartus II to download a `.sof` file including a Cortex-M1 core to the FPGA.

7. Use `arm-none-eabi-sprite -i` to verify that the Sprite can detect the installed Cortex-M1 core.

### 6.7.2. Hardware Breakpoints

The Cortex-M1 core only permits hardware breakpoints to be set in the first 512MB of its address space. Because both external SRAM and flash memory are located at higher addresses, you cannot set hardware breakpoints in these memory regions.

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