Computer Architecture

• Instructor: Jim Huang (黃敬群) <jserv.tw@gmail.com>
• Facebook Group: https://www.facebook.com/groups/system.software2021/
• Policy
  • Follow the classes: CS 61C at UC Berkeley, CS152/252: Computer Architecture
• Course grading
  • Quiz (20%), Homework (40%), Final Project (40%)

Computer Architecture (Fall 2021)

• Week 1 (Sep 28): Introduction
  • Course Introduction
  • David Patterson: A New Golden Age for Computer Architecture: History, Challenges and Opportunities / video
    • Article, note
  • David Patterson: From Mainframe CPUs to Neural-Network TPUs and Open RISC-V / video
  • Great Ideas in Computer Architecture, Intro / video
  • Number Representation
  • Floating Point
  • C Memory Management / video
• Week 2 (Oct 5): Quiz + RISC-V
  • Quiz1: C programming, bit-wise operations, number representation, floating-point / Solution
  • Lab0: Web-based Emulators
  • Introduction to RISC-V Assembly language : Arithmetic
    • The RISC-V Instruction Set Manual: Volume I: Unprivileged ISA
  • Intro to Assembly Language and RISC-V / video
• Week 3 (Oct 12): RISC-V / NOTICE: Join the online class via https://youtu.be/FO4r-0iI7hQ
  • Intro to Assembly Language and RISC-V / video
    • RISC-V Assembly Programmer’s Manual
  • RISC-V lw, sw, Decisions I / video
  • RISC-V Decisions II
  • Lab1: RV32I Simulator
  • Assignment: Homework1: RISC-V Assembly and Instruction Pipeline (Due: ?)
• Week 4 (Oct 19): RISC-V
  • Announcement:
    • quiz rescheduled to Oct 6
    • Code Review for Homework 1 on Oct 6
  • More RISC-V Functions / video
  • Compiler, Assembler, Linker, Loader / video
• Week 5 (Oct 26): Quiz + Code Review
  • Quiz2
    • solution
  • Code Review on Homework1: RISC-V Assembly and Instruction Pipeline
• Week 6 (Oct 13): RISC-V and Toolchain
  • Collaborative notes
  • Next week: digital logic
  • Code Review on Homework1: RISC-V Assembly and Instruction Pipeline
  • Lab2: RISC-V RV32I[MA] emulator with ELF support
  • Assignment: Homework2: RISC-V Toolchain (Due: ?)
  • Further reading FPGA design for Software Engineers
  • RISC-V Instruction Formats / video
• Week 7 (Nov 2): Digital Systems
  • nand2tetris / TED Talk
  • Next generation of rv32emu: sysprog21/rv32emu-next
  • Combinational Digital Logic / video
  • Sequential Digital Logic / video
• Week 8 (Nov 9): Datapath
  • Quiz3
    • solution
  • Lab3: Reindeer - RISCV RV32I[M] Soft CPU
  • RISC-V CPU Datapath, Control Intro / video
  • Assignment: Homework3: SoftCPU (Due: ?)
• Week 9 (Nov 16): Control, Pipeline
  • Collaborative notes
  • Announcement: quiz4 on Nov17: CPU datapath, control, pipeline
  • video: Are Computers Still Getting Faster?
  • Single-Cycle CPU Control / video
  • MIT 6.004 L15: Introduction to Pipelining, L16: Processor Pipelining, L17: Implementing Pipelining
• Week 10 (Nov 23): Pipelined Processors
  • News: XuanTie C906 based Allwinner RISC-V processor to power $12+ Linux SBC’s
  • 0 to ASIC
  • RISC-V: Why the ISA battles are not over yet
  • L18: Implementing Pipelined Processors
  • RISC-V 5-Stage Pipeline / Hazards / video
  • Complex Pipelines, Out-of-Order Issue, Register Renaming
• Week 11 (Nov 30): Quiz + Homework Review
  • Quiz4
    • solution
  • 13-Year-Old, Nicholas Sharkey, Creates a RISC-V Core
  • ARM1 vs. Apple M1
• Week 12 (Dec 7): Cache + Virtual Memory
  • Announcement: Quiz on Dec 1 - pipeline, cache and virtual memory
  • Caches: Direct-mapped, set-associative / video
  • Multi-level Caches, Cache Questions / video
  • The golden age of ever-changing computer architecture
  • Virtual Memory / video
• Week13 (Dec 14): Quiz + Virtual Memory
  • Quiz5
    • solution
  • Virtual Memory / video
  • Term projects 2019
    • Implement RISC-V Compressed Instruction Set on rv32emu
    • Implement RISC-V Compressed Instruction Set for Reindeer, based on pull request RV32C support. must be validated on Step CYC10 FPGA board.
    • Contribute to Ripes: pick up pending issues, work on them, and finally send pull request(s).
    • Prepare practical tutorials for VSRTL, thus people can follow the instructions for implementing minimal RISC-V core such as minrv32.
    • Analyze spu32 with Yosys open synthesis suite. Explain how it works and validate it.
    • Analyze VexRiscv. Explain how it works and validate it.
    • Modify Reindeer to allow non-trial interactive games on Step CYC10 FPGA board, based on Reindeer_Step and Zephyr RTOS.
  • Lab4: Cache
    • Reference work
• Week14 (Dec 21): Synchronization
  • Announcement: Quiz on Dec 22
  • Assignment: Homework4: Cache (Due: ?)
  • Operating Systems / video
  • Synchronization / video
  • Thread-Level Parallelism / video
• Week15 (Dec 28): Operating System and RISC-V
  • Term projects 2020
  • video: The Future of Operating Systems on RISC-V / transcript
  • Advanced topics on Synchronization - 1
  • Advanced topics on Synchronization - 2
• Week16 (Jan 4): I/O, cache coherence
  • Term projects 2020
  • Quiz6
    • solution
  • I/O: Devices, Polling, Interrupts / video
    • Traps/Interrupts/Exceptions
    • Trap Handling in 5-Stage Pipeline
  • Multithreading Issues, Cache Coherency / video
  • Cache Coherence / video
    • Modern microprocessors usually have 2 to 8 cores where each core has a private cache for performance
    • Modified/Shared/Invalid (MSI) Protocol, MESI: An Enhanced MSI protocol to increased performance for private read-write data
• Week17 (Jan 11): Modern Processors
  • Modern Processor Architecture / video
  • Introduction to Dynamic Branch Prediction, Advanced Branch Prediction, Tournament Predictors and Branch Prediction Accuracy, Hardware Based Speculation
• Week18 (Jan 18)
  • Review