版本 e8b3947343558ff184a1156bc561cad7bd1703b0
Computer Architecture
- Instructor: Jim Huang (黃敬群)
<jserv.tw@gmail.com> - Facebook Group: https://www.facebook.com/groups/system.software2020/ / 2019 Fall
- Policy
- Follow the classes: CS 61C at UC Berkeley, CS152/252: Computer Architecture
- Course grading
- Quiz (20%), Homework (40%), Final Project (40%)
- Please scan COVID-19 QR-Code each class
- Student Profile Survey
Computer Architecture (Fall 2020)
- Week 1 (Sep 8)
- David Patterson: A New Golden Age for Computer Architecture: History, Challenges and Opportunities / video
- David Patterson: From Mainframe CPUs to Neural-Network TPUs and Open RISC-V / video
- Great Ideas in Computer Architecture, Intro / video
- Number Representation
- Floating Point
- C Memory Management / video
- Week 2 (Sep 15): Quiz + RISC-V
- Quiz1: C programming, bit-wise operations, number representation, floating-point / Solution
- News: NVIDIA to Acquire Arm for $40 Billion, Creating World’s Premier Computing Company for the Age of AI
- Lab0: Web-based Emulators
- Introduction to RISC-V Assembly language : Arithmetic
- Intro to Assembly Language and RISC-V / video
- Week 3 (Sep 22): RISC-V
- Week 4 (Sep 29): RISC-V
- Announcement:
- quiz rescheduled to Oct 6
- Code Review for Homework 1 on Oct 6
- More RISC-V Functions / video
- Compiler, Assembler, Linker, Loader / video
- Announcement:
- Week 5 (Oct 6): Quiz + Code Review
- Quiz2
- Code Review on Homework1: RISC-V Assembly and Instruction Pipeline
- Week 6 (Oct 13): RISC-V and Toolchain
- Code Review on Homework1: RISC-V Assembly and Instruction Pipeline
- Lab2: RISC-V RV32I[MA] emulator with ELF support
- Assignment: Homework2: RISC-V Toolchain (Due: Oct 26)
- Further reading FPGA design for Software Engineers
- RISC-V Instruction Formats / video
- Week 7 (Oct 20): Digital Systems
- Week 8 (Oct 27): Datapath
- Week 9 (Nov 3): Pipeline
- Week 10 (Nov 10): Pipelined Processors
- Week 11 (Nov 17): Cache
- Week 12 (Nov 24): Virtual Memory
- Week13 (Dec 1): State-of-the-Art
mobile computing & Synchronization
- Processors in 5G era: Cortex-A77 + Cortex-A55
- The Race to Exascale at Supercomputer 2019
- Term projects (due date: Jan 5, 2020)
- explore the workings of virtual memory, specifically the TLB and the Page Table
- Implement RISC-V Compressed Instruction Set on rv32emu
- Implement RISC-V Compressed Instruction Set for Reindeer, based on pull request RV32C support. must be validated on Step CYC10 FPGA board.
- Contribute to Ripes: pick up pending issues, work on them, and finally send pull request(s).
- Prepare practical tutorials for VSRTL, thus people can follow the instructions for implementing minimal RISC-V core such as minrv32.
- Analyze spu32 with Yosys open synthesis suite. Explain how it works and validate it.
- Analyze VexRiscv. Explain how it works and validate it.
- Modify Reindeer to allow non-trial interactive games on Step CYC10 FPGA board, based on Reindeer_Step and Zephyr RTOS.
- Synchronization / video
- Week14 (Dec 8): Synchronization
- Week15 (Dec 15): I/O and Cache Coherence
- Announce: Last quiz on Dec 26, Review final project on Jan 2
- I/O:
Devices, Polling, Interrupts / video
- Traps/Interrupts/Exceptions
- Trap Handling in 5-Stage Pipeline
- Cache
Coherence / video
- Modern microprocessors usually have 2 to 8 cores where each core has a private cache for performance
- Modified/Shared/Invalid (MSI) Protocol, MESI: An Enhanced MSI protocol to increased performance for private read-write data
- Modern Processor Architecture / video
- Week16 (Dec 22): Review and Branch Prediction
- Week17 (Dec 29): Term Project Review
