版本 bcfb920f083bdfca9f685523386fdff82d9a27a6
Changes from bcfb920f083bdfca9f685523386fdff82d9a27a6 to 1d873bead44f7e4d38d7b2678d6ffaf82cc67392
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title: SPI
...
Outline
=======
.. image:: /SPI_single_slave.svg
Interface
=========
SPI 匯流排有規範4個腳位
SCLK: serial clock (output from master);
MOSI: master output, slave input (output from master);
MISO: master input, slave output (output from slave);
SS: slave select (active low, output from master).
Operation
=========
Data transmission
-----------------
Clock polarity and phase
~~~~~~~~~~~~~~~~~~~~~~~~
Mode numbers
~~~~~~~~~~~~~
..
may know used structure
guess: interrupt
Independent slave SPI configuration
-----------------------------------
Daisy chain SPI configuration
------------------------------
Valid SPI communication
-----------------------
interrupts
----------
Example of bit-banging the SPI master protocol
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