版本 3b43a2f2be99fe84af25533c1979d51e480b64d0
Changes from 3b43a2f2be99fe84af25533c1979d51e480b64d0 to bcfb920f083bdfca9f685523386fdff82d9a27a6
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title: SPI
...
Outline
=======
Interface
=========
SPI 匯流排有規範4個腳位
SCLK: serial clock (output from master);
MOSI: master output, slave input (output from master);
MISO: master input, slave output (output from slave);
SS: slave select (active low, output from master).
Operation
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Data transmission
-----------------
Clock polarity and phase
~~~~~~~~~~~~~~~~~~~~~~~~
Mode numbers
~~~~~~~~~~~~~
..
may know used structure
guess: interrupt
Independent slave SPI configuration
-----------------------------------
Daisy chain SPI configuration
------------------------------
Valid SPI communication
-----------------------
interrupts
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Example of bit-banging the SPI master protocol
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