Computer Architecture
- Instructor: Jim Huang (黃敬群)
<jserv.tw@gmail.com> - Facebook Group: https://www.facebook.com/groups/system.software2024/
- Policy
- Follow the classes: CS 61C at UC Berkeley, CMU 18-447: Introduction to Computer Architecture
- Course grading
- Quiz (30%), Homework (30%), Final/Term Project (40%)
- Schedule is tentative and subject to change!
Computer Architecture (Fall 2024)
- Week 1 (Sep 10): Introduction
- Announcement
- Despite September 17th being a national holiday for Mid-Autumn Festival, our class will continue as scheduled, and students are required to complete an online quiz. For information on how to participate and access the remote class, please refer to this website.
- Course Introduction
- David Patterson: A New Golden Age for Computer Architecture: History, Challenges and Opportunities / video
- David Patterson: From Mainframe CPUs to Neural-Network TPUs and Open RISC-V / video
- Great Ideas in Computer Architecture / video
- Number Representation / video
- Understanding Floating Point Struggles / Floating Point (video)
- C Memory Management / video
- RISC-V Instructions
- Announcement
- Week 2 (Sep 17): Quiz
- Week 3 (Sep 24): RISC-V
- Announcement:
- Quiz2 is scheduled on Oct 1: Due to the possibility that the classroom capacity may not accommodate the number of enrolled students, additional classrooms may be arranged as test venues. Please make sure to check this page on the evening of September 30th for related announcements.
- 2023 Quiz2: RISC-V assembly and C programming / solution
- 2022 Quiz2: RISC-V assembly and C programming / solution
- 2021 Quiz2: RISC-V assembly and C programming / solution
- Homework 1 is out.
- Code Review for Homework 1 on Oct 8
- Quiz2 is scheduled on Oct 1: Due to the possibility that the classroom capacity may not accommodate the number of enrolled students, additional classrooms may be arranged as test venues. Please make sure to check this page on the evening of September 30th for related announcements.
- Principles of this course
- Intro to RISC-V / video
- RISC-V Data Transfer / video
- RISC-V Decision Making and Logical Operations / video
- RISC-V Procedures / video
- Lab0: Web-based Emulators
- Lab1: RV32I Assembly
- Assignment: Homework1: RISC-V Assembly and Instruction Pipeline (Due: Oct 14, 2024)
- Announcement:
- Week 4 (Oct 1): Quiz + RISC-V
- Announcement
- Due to the impact of Typhoon Krathon, Quiz 2 will be conducted online instead of in-person. Please refresh this web page to obtain the latest information on how to participate in the online quiz and attend the course remotely.
- Access the live-streamed course on YouTube. Watch the live stream carefully: Quiz 2 participation instructions will be provided during the broadcast.
- Quiz2: RISC-V assembly and C programming / solution
- Fixed-point Arithmetic
- RISC-V Instruction Formats Part I / video
- RISC-V Instruction Formats Part II / video
- Announcement
- Week 5 (Oct 8): RV32I + Code Review
- Review: RISC-V Architecture Instruction Encoding
- Revisit the RV32I specification and instruction encoding, as they serve as the foundation for implementing RISC-V processor cores in HDL.
- The system instructions:
ecall,ebreak, andcsr*. - online tool for RISC-V Instruction Encoder/Decoder / source code
- Recursion as a Problem-Solving Technique
- Code Review on Homework1: RISC-V Assembly and Instruction Pipeline
- Review: RISC-V Architecture Instruction Encoding
- Week 6 (Oct 15): Toolchain + Digital Systems
- Announcement
- Quiz 3 is scheduled for Oct 22 and will cover RISC-V assembly programming, software optimizations, instruction encoding, sequential logic, and combinational logic.
- Compiling, Assembling, Linking, and Loading / video-1 + video-2
- Lab2: RISC-V + VENUS / slides
- Binary marble adding machine / video
- Yes, you can implement a few logic-like elements without electricity.
- Logic gates are primarily implemented using diodes or transistors acting as electronic switches, but can also be constructed using vacuum tubes, electromagnetic relays (relay logic), fluidic logic, pneumatic logic, optics, molecules, or even mechanical elements. Now, most logic gates are made from MOSFETs (metal–oxide–semiconductor field-effect transistors).
- Synchronous Digital Systems (SDS) / video
- Combinational Logic / video
- sequential logic is a type of logic circuit whose output depends on the present value of its input signals and on the sequence of past inputs, the input history.
- SDS State / video
- Combinational Logic Blocks / video
- Announcement
- Week 7 (Oct 22): Quiz
- Week 8 (Oct 29): Review + Datapath and Control
- Announcement:
- Homework 2 is undergoing significant revisions. Please keep an eye on your email for updates.
- The instructor has been grappling with the LLM for several weeks though.
- “What I cannot create, I do not understand.” - On Richard Feynman’s blackboard at the time of his death in 1988 / Build Your Own X
- Revisit Quiz 3
- RISC-V Datapath I / video
- Announcement:
- Week 9 (Nov 5): Datapath and Control + Pipeline
- Announcement:
- Homework 2 is out. Deadline: Nov 18, 2024
- video: Are Computers Still Getting Faster?
- video: Circuits recap
- RISC-V Datapath II / video
- RISC-V Processor Design Control / video
- Constructing Hardware in a Scala Embedded Language (Chisel) is an open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs.
- slides
- Finite impulse response (FIR)
- Learn Chisel online!
- Please run the cell blocks by either pressing SHIFT+ENTER on your keyboard
- MIT 6.191 L15: Introduction to Pipelining, L16: Processor Pipelining
- Announcement:
- Week 10 (Nov 12): Pipelined Processors
- Announcement:
- Next week, we will continue reviewing all the assignments.
- Quiz 4 is scheduled next week.
- The next homework assignment will be given out next week, along with Quiz 4. Please review last year’s homework to get familiar with the procedure and expectations.
- rv32emu development, capable of running Linux kernel smoothly (#508)
- 0 to ASIC
- L16: Processor Pipelining, L17: Implementing Pipelining, L18: Implementing Pipelined Processors / note
- RISC-V 5-Stage Pipeline / video-1, video-2, video-3
- Lab3: Construct a single-cycle CPU with Chisel
- Announcement:
- Week 11 (Nov 19): Quiz + Homework Review
- Week 12 (Nov 26): Cache
- Announcement
- Quiz 5 is scheduled on Dec 10
- This semester, we will conduct 7 quizzes. Out of these, the best 4 will be selected for grading purposes.
- The instructor will submit the grades on the school’s designated deadline (Jan 17, 2024) for grade registration. This means that students will have ample time to dedicate to the final project assigned in this course.
- Caches: Direct-mapped, set-associative / video
- Multi-level Caches, Cache Questions / video
- Lab4: Cache
- Recall: The golden age of ever-changing computer architecture
- Announcement
- Week13 (Dec 3): Virtual Memory + Operating System + Vector Extension
- Announcement:
- Term projects will be listed on Dec 5. Term projects of 2022
- Virtual Memory / UCB: Virtual Memory / video
- Operating Systems / video
- Freestanding RISC-V Programs
- RISC-V Vector extension
- Announcement:
- Week14 (Dec 10): Quiz + Synchronization
- Announcement:
- Check the listing of final/term projects and fill in your names.
- Quiz5: pipelined processor + cache + virtual memory / solution
- Virtual Memory / UCB: Virtual Memory / video
- Apple Silicon Guide
- Debunking CISC vs RISC code density
- Synchronization
- Please check your operating system textbook for such topic.
- Announcement:
- Week15 (Dec 17): Operating System, Multithreading
- Announcement:
- Quiz6 is scheduled on Dec 24
- 2022-Quiz6: pipelined processor + cache + virtual memory / solution
- 2021-Quiz7 / solution
- 2021-Quiz6 / solution
- 2020-Quiz6 / solution
- Quiz6 is scheduled on Dec 24
- Synchronization
- Please check your operating system textbook for such topic.
- Multithreading Issues + Cache Coherency / video
- Let’s skip OpenMP part
- video: The Future of Operating Systems on RISC-V / transcript
- Multithreaded Application Synchronization Part I / Part II
- Taken from CSCI 463: Computer Architecture and Systems Organization
- RISC-V AMOSWAP instruction
- RISC-V spec references the word ‘hart’ - what does ‘hart’ mean?
- Announcement:
- Week16 (Dec 24): Quiz + Memory Model, Synchronization, I/O
- Quiz6 / solution
- Memory Model / slides
- Advanced topics on Synchronization - 1
- Advanced topics on Synchronization - 2
- I/O: Devices, Polling, Interrupts / video
- Traps/Interrupts/Exceptions
- Trap Handling in 5-Stage Pipeline
- Week17 (Dec 31): Modern Processors
- Announcements
- Due to the instructor’s significant involvement in a confidential project, there has been limited participation in this course. Consequently, the instructor proposes a modification to the course grading structure.
- The new breakdown will be as follows: Quiz (30%), Homework (30%), Final/Term Project (25%), and an additional “Base” component (15%). This “Base” component ensures that each student’s starting score is at least 15%.
- Quiz7 is scheduled on Jan 7, 2024
- Due to the instructor’s significant involvement in a confidential project, there has been limited participation in this course. Consequently, the instructor proposes a modification to the course grading structure.
- rv32emu introduces tier-1 JIT compiler to accelerate RISC-V simulation.
- Execute
make ENABLE_JIT=1 clean alland then runbuild/rv32emu build/smolnes.elfto play NES games.
- Execute
- listing of final/term projects
- You must provide the materials and demonstrate to the lecturer before Jan 14, 2023.
- Summarize what you did and send email to
<jserv.tw@gmail.com>.
- Modern Processor Architecture
- Introduction to Dynamic Branch Prediction, Advanced Branch Prediction
- Announcements
- Week 18 (Jan 7): Modern Processors
- Quiz7 / solution
- Tournament Predictors and Branch Prediction Accuracy
- Project: Analyze and improve srv32
- Hardware Based Speculation
- Case study: SoomRV - simple superscalar out-of-order RISC-V core. It can execute up to 4 instructions per cycle and is able to boot Linux.
- RISC vs. CISC by John Mashey, one of the founders of the Standard Performance Evaluation Corporation (SPEC) benchmarking group.
