Computer Architecture
- Instructor: Jim Huang (黃敬群)
<jserv.tw@gmail.com> - Facebook Group: https://www.facebook.com/groups/system.software2023/
- Policy
- Follow the classes: CS 61C at UC Berkeley, CS152/252: Computer Architecture
Computer Architecture (Fall 2023)
- Week 1 (Sep 5): Introduction
- Course Introduction
- David Patterson: A New Golden Age for Computer Architecture: History, Challenges and Opportunities / video
- David Patterson: From Mainframe CPUs to Neural-Network TPUs and Open RISC-V / video
- Great Ideas in Computer Architecture, Intro / video
- Number Representation / video
- Floating Point / video
- C Memory Management / video
- Week 2 (Sep 12): Quiz + RISC-V / online via YouTube
- Announcement
- There is an online quiz from 10:50 AM to 11:59 AM.
- The first assignment, consisting of RISC-V assembly programming, will be given next week.
- Quiz1: C programming, bit-wise operations, number representation, floating-point / Solutions
- RISC-V Instructions
- Announcement
- Week 3 (Sep 19): RISC-V
- Announcement:
- Quiz2 is scheduled on Sep 26
- 2022 Quiz2: RISC-V assembly and C programming / solution
- 2021 Quiz2: RISC-V assembly and C programming / solution
- Homework 1 is out.
- Code Review for Homework 1 on Oct 3
- Quiz2 is scheduled on Sep 26
- Apple A17 Pro
- 19 billion transistors compared to 16 billion on the A16. further reading
- graphics benchmark
- ARM1 (1985) vs. Apple M1 Max (2021)
- Apple Announces M1 Pro & M1 Max: Giant New Arm SoCs with All-Out Performance
- RISC-V Summit China 2023 / slides
- Intro to Assembly Language and RISC-V / video
- RISC-V Data Transfer / video
- RISC-V Decision Making
- Functions Calls with RISC-V / video
- Lab0: Web-based Emulators
- Lab1: RV32I Assembly
- Assignment: Homework1: RISC-V Assembly and Instruction Pipeline (Due: Oct 10, 2023)
- Announcement:
- Week 4 (Sep 26): Quiz + RISC-V
- Errata
- 2023 Quiz1: Additional
x += (x >> 32)statement in Problem A
- 2023 Quiz1: Additional
- Quiz2: RISC-V assembly and C programming / solution
- Fixed-point Arithmetic
- NASA, Microchip, SiFive Announces Partnership for RISC-V Spaceflight Computing Platform
- ST, CAES team on octacore RISC-V space chip with selectable cores
- Calling Convention for RISC-V / video
- CALL = Compiling, Assembling, Linking, and Loading / video
- Errata
- Week 5 (Oct 3): Code Review + RISC-V Instruction Format + GNU Toolchain
- Announcement
- Homework2: RISC-V Toolchain is out.
- Code Review on Homework1: RISC-V Assembly and Instruction Pipeline
- Lab2: RISC-V RV32I[MACF] emulator with ELF support
- Assignment: Homework2: RISC-V Toolchain (Due: Oct 31)
- RISC-V Instruction Formats Part I / Part II / video
- Announcement
- Week 6 (Oct 10): National Day | make up a lesson on Oct 12 night via YouTube
- Announcement:
- Given the consistent progress of the lecture, we will schedule a makeup lesson for 19:30 on October 12th via YouTube.
- Homework2: RISC-V Toolchain is out. (Due: Oct 31)
- RISC-V Instruction Formats Part I / Part II / video
- Further reading FPGA design for Software Engineers
- Announcement:
- Week 7 (Oct 17): Digital Systems
- Announcement:
- Quiz 3 is scheduled for Oct 24 and will cover RISC-V assembly programming, software optimizations, instruction encoding, sequential logic, and combinational logic.
- Code Review for Homework 2 is scheduled for Oct 24.
- Binary marble adding machine / video
- Yes, you can implement a few logic-like elements without electricity.
- Logic gates are primarily implemented using diodes or transistors acting as electronic switches, but can also be constructed using vacuum tubes, electromagnetic relays (relay logic), fluidic logic, pneumatic logic, optics, molecules, or even mechanical elements. Now, most logic gates are made from MOSFETs (metal–oxide–semiconductor field-effect transistors).
- nand2tetris
- Synchronous Digital Systems (SDS), Boolean Algebra / video
- sequential logic is a type of logic circuit whose output depends on the present value of its input signals and on the sequence of past inputs, the input history.
- State, Combinational Logic / video
- Announcement:
- Week 8 (Oct 24): Quiz + Datapath and Control
- Quiz3: RISC-V programming and instruction encoding + Digital systems / solution
- RISC-V CPU Datapath / video
- Week 9 (Oct 31): online via YouTube; Datapath and Control + Pipeline
- Announcement:
- New quiz is scheduled on Nov 14.
- Code Review for Homework 2 is scheduled on N14.
- video: Are Computers Still Getting Faster?
- video: Circuits recap
- Constructing Hardware in a Scala Embedded Language (Chisel) is an open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs.
- slides
- Finite impulse response (FIR)
- Learn Chisel online!
- Please run the cell blocks by either pressing SHIFT+ENTER on your keyboard
- RISC-V CPU Datapath / video
- Single-Cycle CPU Control / video
- MIT 6.191 L15: Introduction to Pipelining, L16: Processor Pipelining
- Announcement:
- Week 10 (Nov 7): Pipelined Processors
- Announcement:
- Homework3 is out.
- Next week, we will continue reviewing all the assignments.
- Quiz4 is scheduled next week.
- rv32emu development
- 0 to ASIC
- L16: Processor Pipelining, L17: Implementing Pipelining, L18: Implementing Pipelined Processors / note
- RISC-V 5-Stage Pipeline / Hazards / video
- Lab3: Construct a single-cycle CPU with Chisel
- Assignment: Homework3: Single-cycle CPU in Chisel (Due: Dec 1, 2023)
- Announcement:
- Week 11 (Nov 14): Quiz + Homework Review
- Quiz4: RISC-V programming + datapath + control + pipelined processor / solution
- Homework1, Homework2
- Complex Pipelines, Out-of-Order Issue, Register Renaming
- Week 12 (Nov 21): Cache
- Announcement
- The class scheduled for Nov 28 will be conducted online and will be available via YouTube.
- Quiz 5 is scheduled on Dec 5
- This semester, we will conduct 7 quizzes. Out of these, the best 4 will be selected for grading purposes.
- The instructor will submit the grades on the school’s designated deadline (Jan 17, 2024) for grade registration. This means that students will have ample time to dedicate to the final project assigned in this course.
- Caches: Direct-mapped, set-associative / video
- Multi-level Caches, Cache Questions / video
- Lab4: Cache
- Recall: The golden age of ever-changing computer architecture
- Announcement
- Week13 (Nov 28): online via YouTube: Virtual Memory + Operating System + Vector Extension
- Announcement:
- Term projects will be listed on Dec 5. Term projects of 2022
- Virtual Memory / UCB: Virtual Memory / video
- Operating Systems / video
- Freestanding RISC-V Programs
- RISC-V Vector extension
- Announcement:
- Week14 (Dec 5): Quiz + Synchronization
- Announcement:
- Check the listing of final/term projects and fill in your names.
- Quiz5: pipelined processor + cache + virtual memory / solution
- Virtual Memory / UCB: Virtual Memory / video
- Apple Silicon Guide
- Debunking CISC vs RISC code density
- Synchronization
- Please check your operating system textbook for such topic.
- Announcement:
- Week15 (Dec 12): Operating System, Multithreading
- Announcement:
- Quiz6 is scheduled on Dec 19
- 2022-Quiz6: pipelined processor + cache + virtual memory / solution
- 2021-Quiz7 / solution
- 2021-Quiz6 / solution
- 2020-Quiz6 / solution
- Quiz6 is scheduled on Dec 19
- Synchronization
- Please check your operating system textbook for such topic.
- Multithreading Issues + Cache Coherency / video
- Let’s skip OpenMP part
- video: The Future of Operating Systems on RISC-V / transcript
- Multithreaded Application Synchronization Part I / Part II
- Taken from CSCI 463: Computer Architecture and Systems Organization
- RISC-V AMOSWAP instruction
- RISC-V spec references the word ‘hart’ - what does ‘hart’ mean?
- Announcement:
- Week16 (Dec 19): online via YouTube | Quiz + Memory Model, Synchronization, I/O
- Quiz6 / solution
- Memory Model / slides
- Advanced topics on Synchronization - 1
- Advanced topics on Synchronization - 2
- I/O: Devices, Polling, Interrupts / video
- Traps/Interrupts/Exceptions
- Trap Handling in 5-Stage Pipeline
- Week17 (Dec 26): Modern Processors
- Announcements
- Due to the instructor’s significant involvement in a confidential project, there has been limited participation in this course. Consequently, the instructor proposes a modification to the course grading structure.
- The new breakdown will be as follows: Quiz (30%), Homework (30%), Final/Term Project (25%), and an additional “Base” component (15%). This “Base” component ensures that each student’s starting score is at least 15%.
- Quiz7 is scheduled on Jan 2, 2024
- Due to the instructor’s significant involvement in a confidential project, there has been limited participation in this course. Consequently, the instructor proposes a modification to the course grading structure.
- SSE2NEON v1.7 is out.
- rv32emu introduces tier-1 JIT compiler to accelerate RISC-V simulation.
- Execute
make ENABLE_JIT=1 clean alland then runbuild/rv32emu build/smolnes.elfto play NES games.
- Execute
- listing of final/term projects
- You must provide the materials and demonstrate to the lecturer before Jan 14, 2023.
- Summarize what you did and send email to
<jserv.tw@gmail.com>.
- Modern Processor Architecture
- Introduction to Dynamic Branch Prediction, Advanced Branch Prediction
- Announcements
- Week 18 (Jan 2): Modern Processors
- Quiz7 / solution
- Tournament Predictors and Branch Prediction Accuracy
- Project: Analyze and improve srv32
- Hardware Based Speculation
- Case study: SoomRV - simple superscalar out-of-order RISC-V core. It can execute up to 4 instructions per cycle and is able to boot Linux.
- RISC vs. CISC by John Mashey, one of the founders of the Standard Performance Evaluation Corporation (SPEC) benchmarking group.
Computer Architecture (Fall 2022)
- Week 1 (Sep 6): Introduction / Online via YouTube
- Course Introduction
- David Patterson: A New Golden Age for Computer Architecture: History, Challenges and Opportunities / video
- David Patterson: From Mainframe CPUs to Neural-Network TPUs and Open RISC-V / video
- Great Ideas in Computer Architecture, Intro / video
- Number Representation / video
- Floating Point / video
- C Memory Management / video
- Week 2 (Sep 13): Quiz + RISC-V / Online via YouTube
- Quiz1: C programming, bit-wise operations, number representation, floating-point / Solution
- Lab0: Web-based Emulators
- RISC-V Instructions
- Intro to Assembly Language and RISC-V / video
- Week 3 (Sep 20): RISC-V / Online via YouTube
- Week 4 (Sep 27): RISC-V / Online via YouTube
- Announcement:
- Next quiz is scheduled to Oct 4
- Code Review for Homework 1 on Oct 4
- NASA, Microchip, SiFive Announces Partnership for RISC-V Spaceflight Computing Platform
- ST, CAES team on octacore RISC-V space chip with selectable cores
- Apple M1 Pro/Max
- Calling Convention for RISC-V / video
- CALL = Compiling, Assembling, Linking, and Loading / video
- 2021-Quiz2 / solution
- Announcement:
- Week 5 (Oct 4): Quiz + Code Review (Room 4201 (1F) at (old) CSIE Building)
- Quiz2: RISC-V assembly and C programming / solution
- Code Review on Homework1: RISC-V Assembly and Instruction Pipeline
- Week 6 (Oct 11): RISC-V Instruction Format + GNU Toolchain / Online via YouTube
- Next week: digital logic
- Further reading FPGA design for Software Engineers
- Lab2: RISC-V RV32I[MACF] emulator with ELF support
- Assignment: Homework2: RISC-V Toolchain (Due: Oct 31)
- RISC-V Instruction Formats Part I / Part II / video
- Week 7 (Oct 18): Digital Systems / Online via YouTube
- Announcement: New quiz is scheduled on Oct 25
- Binary marble adding machine / video
- Yes, you can implement a few logic-like elements without electricity.
- Logic gates are primarily implemented using diodes or transistors acting as electronic switches, but can also be constructed using vacuum tubes, electromagnetic relays (relay logic), fluidic logic, pneumatic logic, optics, molecules, or even mechanical elements. Now, most logic gates are made from MOSFETs (metal–oxide–semiconductor field-effect transistors).
- nand2tetris
- Synchronous Digital Systems (SDS), Boolean Algebra / video
- sequential logic is a type of logic circuit whose output depends on the present value of its input signals and on the sequence of past inputs, the input history.
- State, Combinational Logic / video
- 2020-Quiz3 / solution
- 2021-Quiz3 / solution
- 2021-Quiz4 / solution
- Week 8 (Oct 25): Datapath and Control + Code Review (Room 4201 (1F) at (old) CSIE Building)
- Quiz3: RISC-V programming and instruction encoding + Digital systems / solution
- RISC-V CPU Datapath / video
- Week 9 (Nov 1): Pipeline / Online via YouTube
- Week 10 (Nov 8): Pipelined Processors / Online via YouTube
- Announcement:
- The next quiz is planned on Nov 15.
- Homework3 SoftCPU is out.
- Next week, we will review all the assignments.
- Recent rv32emu changes
- More descriptions about system calls. See docs/syscall.md
- Implement
clock_gettimesystem call, so that you can callgettimeofday/clock_gettimein C programs. - Implement user-level counters for getting CPU cycle counts in RISC-V programs. See tests/perfcounter for sample usage.
- Better experiences while running Doom and Quake games. You can resize the window and use mouse properly.
- More test programs: jit-bf (JIT assembler for RISC-V), coro (a simple coroutine implementation for RISC-V), mandelbrot (an ASCII-based renderer for Mandelbrot Set, colorized), richards (an operating system task scheduler simulation benchmark), and chacha20 (stream cipher)
- More comments in source files.
- 0 to ASIC
- L16: Processor Pipelining, L17: Implementing Pipelining, L18: Implementing Pipelined Processors / note
- RISC-V 5-Stage Pipeline / Hazards / video
- Lab3: srv32 - RISCV RV32IM Soft CPU
- Assignment: Homework3: SoftCPU (Due: Nov 30, 2022)
- 2020 Quiz4 / solution
- 2021 Quiz5 / solution / annotated with Ripes
- Announcement:
- Week 11 (Nov 15): Quiz + Homework Review (Room 4201 (1F) at (old) CSIE Building)
- Quiz4: RISC-V programming + datapath + control + pipelined processor / solution
- Homework1, Homework2
- Complex Pipelines, Out-of-Order Issue, Register Renaming
- Week 12 (Nov 22): Cache + Virtual Memory / Online via YouTube
- Announcement
- Quiz on Nov 29 - pipeline, cache and virtual memory (partial)
- Term projects will be listed on Nov 29
- Caches: Direct-mapped, set-associative / video
- Multi-level Caches, Cache Questions / video
- The golden age of ever-changing computer architecture
- Virtual Memory / UCB: Virtual Memory / video
- 2021-Qui6 / solution / with Ripes simulation
- 2020-Quiz5 / solution
- Announcement
- Week13 (Nov 29): Quiz + Virtual Memory + Operating System (Room 4201 (1F) at (old) CSIE Building)
- Announcement:
- Be aware of Term projects
- Quiz5: pipelined processor + cache + virtual memory / solution
- Virtual Memory / video
- Lab4: Cache
- Operating Systems / video
- Announcement:
- Week14 (Dec 6): Synchronization / Online via YouTube
- Announcement:
- Quiz6 on Dec 13
- Check the listing of final/term projects and fill in your names.
- Apple Silicon Guide
- Debunking CISC vs RISC code density
- Operating Systems / video
- Synchronization
- Please check your operating system textbook for such topic.
- Thread-Level Parallelism / video
- Let’s skip OpenMP part
- Multithreading Issues + Cache Coherency / video
- 2021 Quiz7 /solution
- 2021 Quiz6 /solution
- 2020 Quiz6 /solution
- Announcement:
- Week15 (Dec 13): suspended
- Announcement:
- Quiz6 will be postponed to Dec 20
- Quiz7 on Dec 27
- Check the listing of final/term projects
- Announcement:
- Week16 (Dec 20): Multithreading, Synchronization, I/O
- Quiz6 / solution
- video: The Future of Operating Systems on RISC-V / transcript
- Freestanding RISC-V Programs
- Multithreaded Application Synchronization Part I
- Multithreaded Application Synchronization Part II
- RISC-V AMOSWAP instruction
- Advanced topics on Synchronization - 1
- Advanced topics on Synchronization - 2
- I/O: Devices, Polling, Interrupts / video
- Traps/Interrupts/Exceptions
- Trap Handling in 5-Stage Pipeline
- Week17 (Dec 27): Modern Processors
- Quiz7 / solution
- listing of final/term projects
- You must provide the materials and demonstrate to the lecturer before Jan 13, 2023.
- Summarize what you did and send email to
<jserv.tw@gmail.com>.
- Modern Processor Architecture
- Introduction to Dynamic Branch Prediction, Advanced Branch Prediction, Tournament Predictors and Branch Prediction Accuracy
- Project: Analyze and improve srv32
- Hardware Based Speculation
- Week 18 (Jan 2): Modern Processors / Online via YouTube
- Modern Processor Architecture
- Introduction to Dynamic Branch Prediction, Advanced Branch Prediction, Tournament Predictors and Branch Prediction Accuracy
- Project: Analyze and improve srv32
- Hardware Based Speculation
- Case study: VRoom - very high end RISC-V implementation, cloud server class, out of order, super scalar, speculative, up to 8 IPC
- RISC vs. CISC by John Mashey, one of the founders of the Standard Performance Evaluation Corporation (SPEC) benchmarking group.
Computer Architecture (Fall 2021)
- Week 1 (Sep 28): Introduction
- Course Introduction
- David Patterson: A New Golden Age for Computer Architecture: History, Challenges and Opportunities / video
- David Patterson: From Mainframe CPUs to Neural-Network TPUs and Open RISC-V / video
- Great Ideas in Computer Architecture, Intro / video
- Number Representation
- Floating Point
- C Memory Management / video
- Week 2 (Oct 5): Quiz + RISC-V
- Quiz1: C programming, bit-wise operations, number representation, floating-point / Solution
- Lab0: Web-based Emulators
- Introduction to RISC-V Assembly language : Arithmetic
- Intro to Assembly Language and RISC-V / video
- Week 3 (Oct 12): RISC-V
- Week 4 (Oct 19): RISC-V
- Announcement:
- Next quiz is scheduled to Oct 26
- Code Review for Homework 1 on Oct 26
- We might be in a physical classroom next week. Please check the latest announcement via email.
- Apple M1 Pro/Max
- More RISC-V Functions / video
- Compiler, Assembler, Linker, Loader / video
- 2020-Quiz2
- Announcement:
- Week 5 (Oct 26): Quiz + Code Review (Room 4201 (1F) at (old) CSIE Building)
- Quiz2: RISC-V assembly and C programming / solution
- Code Review on Homework1: RISC-V Assembly and Instruction Pipeline
- Week 6 (Nov 2): RISC-V Instruction Format + GNU Toolchain + Code Review (Room 4201 (1F) at (old) CSIE Building)
- Next week: digital logic
- Code Review on Homework1: RISC-V Assembly and Instruction Pipeline
- Lab2: RISC-V RV32I[MA] emulator with ELF support
- Assignment: Homework2: RISC-V Toolchain (Due: Nov 15)
- Further reading FPGA design for Software Engineers
- RISC-V Instruction Formats / video
- Week 7 (Nov 9): Digital Systems
- Announcement: New quiz on Nov 16
- Next generation of rv32emu: sysprog21/rv32emu-next
- Combinational Digital Logic / video
- Sequential Digital Logic / video
- 2020-Quiz3
- Week 8 (Nov 16): Datapath and Control
- Announcement: Due to internal problems of HackMD (pictures were not shown), we would take new scoring method to eliminate the impact. Next week, we have an additional quiz dedicated to Combinational and Sequential Digital Logic.
- Quiz3: RISC-V programming and instruction encoding + Digital systems / solution
- RISC-V CPU Datapath, Control Intro / video
- Single-Cycle CPU Control / video
- Week 9 (Nov 23): Pipeline
- Announcement:
- Next quiz is scheduled to Dec 7
- Quiz4: Digital systems / solution
- video: Are Computers Still Getting Faster?
- MIT 6.004 L15: Introduction to Pipelining, L16: Processor Pipelining, L17: Implementing Pipelining
- slides: Introduction to Pipelining
- slides: Pipelined Processors
- note
- Announcement:
- Week 10 (Nov 30): Pipelined Processors
- Announcement:
- Next quiz is scheduled to Dec 7
- Homework3: SoftCPU is out.
- Next week, we will review all the assignments.
- 0 to ASIC
- L16: Processor Pipelining, L17: Implementing Pipelining, L18: Implementing Pipelined Processors / note
- slides: Pipelined Processors
- slides: Pipelined Processors Data and Control Hazards
- RISC-V 5-Stage Pipeline / Hazards / video
- Complex Pipelines, Out-of-Order Issue, Register Renaming
- Lab3: srv32 - RISCV RV32IM Soft CPU
- Assignment: Homework3: SoftCPU (Due: Dec 20, 2021)
- 2020 Quiz4
- Announcement:
- Week 11 (Dec 7): Quiz + Homework Review
- Week 12 (Dec 14): Cache + Virtual Memory
- Announcement: Quiz on Dec 21 - pipeline, cache and virtual memory
- Caches: Direct-mapped, set-associative / video
- Multi-level Caches, Cache Questions / video
- The golden age of ever-changing computer architecture
- Cerebras announced a system which connects multiple integrated circuits (commonly called “chips”) into a neural network with many connections in Aug 2021. It enables a single system to support AI models with more than 120 trillion parameters.
- Virtual Memory / video
- UCB: Virtual Memory / video
- 2020-Quiz5 / solution
- Week13 (Dec 21): Quiz + Virtual Memory + Operating System
- Announcement:
- Be aware of term projects.
- Next week, we will review all the assignments.
- Quiz6: pipelined processor + cache + virtual memory / solution
- Virtual Memory / video
- Lab4: Cache
- Operating Systems / video
- Term projects 2020
- Announcement:
- Week14 (Dec 28): Synchronization
- Announcement:
- Quiz on Jan 11
- Your grades will be delivered on Jan 21, 2022
- Check the listing of final/term projects
- Term projects 2021
- Synchronization / video
- Thread-Level Parallelism / video
- Let’s skip OpenMP part
- Announcement:
- Week15 (Jan 4): Operating System and RISC-V, cache coherence
- Announcement:
- Quiz7 on Jan 11
- Check the listing of final/term projects
- video: The Future of Operating Systems on RISC-V / transcript
- Multithreading Issues, Cache Coherency / video
- Let’s skip OpenMP part
- Freestanding RISC-V Programs
- Multithreaded Application Synchronization Part I
- Multithreaded Application Synchronization Part II
- RISC-V AMOSWAP instruction
- Advanced topics on Synchronization - 1
- Advanced topics on Synchronization - 2
- 2020 Quiz6
- Announcement:
- Week16 (Jan 11): I/O
- Quiz7 / solution
- I/O: Devices, Polling, Interrupts / video
- Traps/Interrupts/Exceptions
- Trap Handling in 5-Stage Pipeline
- Week17 (Jan 18): Modern Processors
Computer Architecture (Fall 2020)
Week 1
- David Patterson: A New Golden Age for Computer Architecture: History, Challenges and Opportunities / video
- David Patterson: From Mainframe CPUs to Neural-Network TPUs and Open RISC-V / video
- Great Ideas in Computer Architecture, Intro / video
- Number Representation
- Floating Point
- C Memory Management / video
Week 2: Quiz + RISC-V
- Quiz1: C programming, bit-wise operations, number representation, floating-point / Solution
- News: NVIDIA to Acquire Arm for $40 Billion, Creating World’s Premier Computing Company for the Age of AI
- Lab0: Web-based Emulators
- Introduction to RISC-V Assembly language : Arithmetic
- Intro to Assembly Language and RISC-V / video
Week 3: RISC-V
Week 4: RISC-V
- Announcement:
- quiz rescheduled to Oct 6
- Code Review for Homework 1 on Oct 6
- More RISC-V Functions / video
- Compiler, Assembler, Linker, Loader / video
- Announcement:
Week 5: Quiz + Code Review
- Quiz2
- Code Review on Homework1: RISC-V Assembly and Instruction Pipeline
Week 6: RISC-V and Toolchain
- Collaborative notes
- Next week: digital logic
- Code Review on Homework1: RISC-V Assembly and Instruction Pipeline
- Lab2: RISC-V RV32I[MA] emulator with ELF support
- Assignment: Homework2: RISC-V Toolchain (Due: Oct 26)
- Further reading FPGA design for Software Engineers
- RISC-V Instruction Formats / video
Week 7: Digital Systems
- nand2tetris / TED Talk
- Next generation of rv32emu: sysprog21/rv32emu-next
- Combinational Digital Logic / video
- Sequential Digital Logic / video
Week 8: Datapath
- Quiz3
- Lab3: Reindeer - RISCV RV32I[M] Soft CPU
- RISC-V CPU Datapath, Control Intro / video
- Assignment: Homework3: SoftCPU (Due: Nov 16)
Week 9: Control, Pipeline
- Collaborative notes
- Announcement: quiz4 on Nov17: CPU datapath, control, pipeline
- video: Are Computers Still Getting Faster?
- Single-Cycle CPU Control / video
- MIT 6.004 L15: Introduction to Pipelining, L16: Processor Pipelining, L17: Implementing Pipelining
Week 10: Pipelined Processors
Week 11: Quiz + Homework Review
Week 12: Cache + Virtual Memory
- Announcement: Quiz on Dec 1 - pipeline, cache and virtual memory
- Caches: Direct-mapped, set-associative / video
- Multi-level Caches, Cache Questions / video
- The golden age of ever-changing computer architecture
- Virtual Memory / video
Week13: Quiz + Virtual Memory
- Quiz5
- Virtual Memory / video
- Term projects 2019
- Implement RISC-V Compressed Instruction Set on rv32emu
- Implement RISC-V Compressed Instruction Set for Reindeer, based on pull request RV32C support. must be validated on Step CYC10 FPGA board.
- Contribute to Ripes: pick up pending issues, work on them, and finally send pull request(s).
- Prepare practical tutorials for VSRTL, thus people can follow the instructions for implementing minimal RISC-V core such as minrv32.
- Analyze spu32 with Yosys open synthesis suite. Explain how it works and validate it.
- Analyze VexRiscv. Explain how it works and validate it.
- Modify Reindeer to allow non-trial interactive games on Step CYC10 FPGA board, based on Reindeer_Step and Zephyr RTOS.
- Lab4: Cache
Week14: Synchronization
- Announcement: Quiz on Dec 22
- Assignment: Homework4: Cache (Due: Dec 26)
- Operating Systems / video
- Synchronization / video
- Thread-Level Parallelism / video
Week15: Operating System and RISC-V
- Term projects 2020
- You must provide the materials and demonstrate to the lecturer before Jan 19, 2021
- video: The Future of Operating Systems on RISC-V / transcript
- Advanced topics on Synchronization - 1
- Advanced topics on Synchronization - 2
- Term projects 2020
Week16: I/O, cache coherence
- Term projects 2020
- You must provide the materials and demonstrate to the lecturer before Jan 19, 2021
- Quiz6
- I/O: Devices, Polling, Interrupts / video
- Traps/Interrupts/Exceptions
- Trap Handling in 5-Stage Pipeline
- Multithreading Issues, Cache Coherency / video
- Cache Coherence / video
- Modern microprocessors usually have 2 to 8 cores where each core has a private cache for performance
- Modified/Shared/Invalid (MSI) Protocol, MESI: An Enhanced MSI protocol to increased performance for private read-write data
- Term projects 2020
Week17: class will be suspended
Week18
Computer Architecture (Fall 2019)
Week 1 (Sep 12)
Week 2 (Sep 19): Quiz
Week 3 (Sep 26): Suspension
Week 4 (Oct 3): RISC-V
Week 5 (Oct 10): Holiday
Week 6 (Oct 17): RISC-V and Toolchain
- Lab2: RISC-V RV32I[MA] emulator with ELF support
- RISC-V Instruction Formats I / video
- Compilation, Assembly, Linking, Loading
- Assignment: Homework2: RISC-V Toolchain (Due: Oct 30, 2019)
- Further reading FPGA design for Software Engineers
Week 7 (Oct 24): RISC-V and Digital Systems
- ANN: Next week, we will have another quiz.
- RISC-V Procedures
- Practice: RISC-V Control Flow, CALL, RISC-V Procedures
- Practice: CS 152 Computer Architecture and Engineering - Midterm #1
- Problem 2: Microcoding: writing microcode for a bus-based implementation of the RISC-V machine
- Problem 3: 5-Stage Pipelines
- Intro to Synchronous Digital Systems / video
- State
- Combinational Logic
- Combinational Logic Blocks / video
- Practice: Logic
Week 8 (Oct 31): Datapath
- Lab3: Reindeer - RISCV RV32I[M] Soft CPU
- Single-Cycle CPU Datapath I
- Single-Cycle CPU Datapath II
- Single-Cycle CPU Control / video
- Quiz
- Assignment: Homework3: SoftCPU (Due: Nov 20, 2019)
Week 9 (Nov 7): Pipeline
Week 10 (Nov 14): Pipelined Proccesors
Week 11 (Nov 21): Cache
Week 12 (Nov 28): Virtual Memory
Week13 (Dec 5): State-of-the-Art mobile computing & Synchronization
- Processors in 5G era: Cortex-A77 + Cortex-A55
- The Race to Exascale at Supercomputer 2019
- Term projects (due date: Jan 5, 2020)
- explore the workings of virtual memory, specifically the TLB and the Page Table
- Implement RISC-V Compressed Instruction Set on rv32emu
- Implement RISC-V Compressed Instruction Set for Reindeer, based on pull request RV32C support. must be validated on Step CYC10 FPGA board.
- Contribute to Ripes: pick up pending issues, work on them, and finally send pull request(s).
- Prepare practical tutorials for VSRTL, thus people can follow the instructions for implementing minimal RISC-V core such as minrv32.
- Analyze spu32 with Yosys open synthesis suite. Explain how it works and validate it.
- Analyze VexRiscv. Explain how it works and validate it.
- Modify Reindeer to allow non-trial interactive games on Step CYC10 FPGA board, based on Reindeer_Step and Zephyr RTOS.
- Synchronization / video
Week14 (Dec 12): Synchronization
Week15 (Dec 19): I/O and Cache Coherence
- Announce: Last quiz on Dec 26, Review final project on Jan 2
- I/O: Devices, Polling, Interrupts / video
- Traps/Interrupts/Exceptions
- Trap Handling in 5-Stage Pipeline
- Cache Coherence / video
- Modern microprocessors usually have 2 to 8 cores where each core has a private cache for performance
- Modified/Shared/Invalid (MSI) Protocol, MESI: An Enhanced MSI protocol to increased performance for private read-write data
- Modern Processor Architecture / video
Week16 (Dec 26): Review and Branch Prediction
Week17 (Jan 2): Term Project Review
