Outline

.. image:: /SPI_single_slave.svg Interface ========= SPI 匯流排有規範4個腳位 SCLK: serial clock (output from master);

MOSI: master output, slave input (output from master);

MISO: master input, slave output (output from slave);

SS: slave select (active low, output from master).

Operation

Data transmission

Clock polarity and phase ~~~~~~~~~~~~~~~~~~~~~~~~ Mode numbers ~~~~~~~~~~~~~ .. may know used structure guess: interrupt Independent slave SPI configuration ———————————– Daisy chain SPI configuration —————————— Valid SPI communication ———————– interrupts ———- Example of bit-banging the SPI master protocol ———————————————-