INTRODUCTION ………………. USART(universal synchronous asynchronous receiver transmitter) 通用同步/非同步收發傳輸器，提供了一種靈活的方法及使用NRZ非同步串行資料格式與外部設備之間進行全雙工資料交換。 同時，USART也提供同步的方式半雙工的通信，另外支持LIN (local interconnection network)，Smartcard協定及IrDA (infrared data association紅外通訊技術) SIR ENDEC，Modem(CTS/RTS)的操作。 藉由DMA多重緩衝器的方式，可達到高速資料的通訊。

MAIN FEATURES ……………….

• 全雙工的非同步通訊

• NRZ標準資料格式

• 可程式化的資料長度 (8 or 9 bits)

• 可程式化的停止位元 (1 or 2 bits)

• 提供同步傳輸的CLK信號

• 藉由DMA的多緩衝器資料傳輸，每個USART都能用DMA發送和接收資料

• 獨立的發送器和接收器的enable bit

• 傳輸檢測標誌

– 接收緩衝區滿

– 傳送緩衝區空

– 傳輸結束

• 校驗控制

– 發送校驗位

– 對接收的資料進行校驗

• 4個錯誤檢測標誌

– 溢出錯誤(Overrun error)

– 噪音檢測(Noise detection)

– Frame錯誤

– 校驗錯誤

• 10個中斷源

– CTS改變

– LIN中斷檢測

– 傳送緩衝區空

– 傳送完成

– 接收緩衝區滿

– 空閒線路檢測

– 溢出錯誤

– Frame錯誤

– 噪音錯誤

– 校驗錯誤

• 2種喚醒接收器的方式

• Address bit (MSB, 9th bit)

• Idle line

USART functional description ……………………………

USART BLOCK DIAGRAM

.. image:: /usart_block_diagram.png

USART character description

資料長度根據USART_CR1暫存器中的M位選擇8或9位元(見 Figure 246).

在起始位期間，TX處於低電位，在停止位期間，TX處於高電位。 另外空閒符號則全由’1’組成，後面接著下一個資料的開始位(‘1’的位數也包含資料的停止位元位數)； 中斷符號則全由’0’所組成(包含資料的停止位也是’0’)，在中斷時，發送器會再插入1或2個停止位(‘0’)

.. image:: /idleandbreak.png

Transmitter

The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the transmit enable bit (TE) is set, the data in the transmit shift register is output on the TX pin and the corresponding clock pulses are output on the SCLK pin.

Character transmission

During an USART transmission, data shifts out least significant bit first on the TX pin. In this mode, the USART_DR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 245).

Every character is preceded by a start bit which is a logic level low for one bit period. The character is terminated by a configurable number of stop bits.

The following stop bits are supported by USART: 0.5, 1, 1.5 and 2 stop bits.

Receiver

The USART can receive data words of either 8 or 9 bits depending on the M bit in the USART_CR1 register.

Break character

When a break character is received, the USART handles it as a framing error.

Idle character

When an idle frame is detected, there is the same procedure as a data received character plus an interrupt if the IDLEIE bit is set.

Overrun error

An overrun error occurs when a character is received when RXNE has not been reset. Data can not be transferred from the shift register to the RDR register until the RXNE bit is cleared.

The RXNE flag is set after every byte received. An overrun error occurs if RXNE flag is set when the next data is received or the previous DMA request has not been serviced. When an overrun error occurs:

● The ORE bit is set.

● The RDR content will not be lost. The previous data is available when a read to USART_DR is performed.

● The shift register will be overwritten. After that point, any data received during overrun is lost.

● An interrupt is generated if either the RXNEIE bit is set or both the EIE and DMAR bits are set.

● The ORE bit is reset by a read to the USART_SR register followed by a USART_DR register read operation.

Note: The ORE bit, when set, indicates that at least 1 data has been lost. There are two possibilities:

● if RXNE=1, then the last valid data is stored in the receive register RDR and can be read,

● if RXNE=0, then it means that the last valid data has already been read and thus there is nothing to be read in the RDR. This case can occur when the last valid data is read in the RDR at the same time as the new (and lost) data is received. It may also occur when the new data is received during the reading sequence (between the USART_SR register read access and the USART_DR read access).

Selecting the proper oversampling method

The receiver implements different user-configurable oversampling techniques (except in synchronous mode) for data recovery by discriminating between valid incoming data and noise.

The oversampling method can be selected by programming the OVER8 bit in the USART_CR1 register and can be either 16 or 8 times the baud rate clock (Figure 250 and Figure 251).

Depending on the application:

● select oversampling by 8 (OVER8=1) to achieve higher speed (up to fPCLK/8). In this case the maximum receiver tolerance to clock deviation is reduced (refer to Section 26.3.5: USART receiver tolerance to clock deviation on page 760)

● select oversampling by 16 (OVER8=0) to increase the tolerance of the receiver to clock deviations. In this case, the maximum speed is limited to maximum fPCLK/16 Programming the ONEBIT bit in the USART_CR3 register selects the method used to evaluate the logic level. There are two options:

● the majority vote of the three samples in the center of the received bit. In this case, when the 3 samples used for the majority vote are not equal, the NF bit is set

● a single sample in the center of the received bit

Depending on the application:

– select the three samples’ majority vote method (ONEBIT=0) when operating in a noisy environment and reject the data when a noise is detected (refer to Figure 105) because this indicates that a glitch occurred during the sampling.

– select the single sample method (ONEBIT=1) when the line is noise-free to increase the receiver’s tolerance to clock deviations (see Section 26.3.5: USART receiver tolerance to clock deviation on page 760). In this case the NF bit will never be set.

When noise is detected in a frame:

● The NF bit is set at the rising edge of the RXNE bit.

● The invalid data is transferred from the Shift register to the USART_DR register.

● No interrupt is generated in case of single byte communication. However this bit rises at the same time as the RXNE bit which itself generates an interrupt. In case of multibuffer communication an interrupt will be issued if the EIE bit is set in the USART_CR3 register.

The NF bit is reset by a USART_SR register read operation followed by a USART_DR register read operation.

Note: Oversampling by 8 is not available in the Smartcard, IrDA and LIN modes. In those modes, the OVER8 bit is forced to ‘0 by hardware.

.. image:: /oversampling16.png

.. image:: /oversampling8.png

.. image:: /noisedetection.png

.. image:: /noisedetectionsampledata.png

Fractional baud rate generation

The baud rate for the receiver and transmitter (Rx and Tx) are both set to the same value as programmed in the Mantissa and Fraction values of USARTDIV.

.. image:: /baud.png

USARTDIV is an unsigned fixed point number that is coded on the USART_BRR register.

● When OVER8=0, the fractional part is coded on 4 bits and programmed by the DIV_fraction[3:0] bits in the USART_BRR register

● When OVER8=1, the fractional part is coded on 3 bits and programmed by the DIV_fraction[2:0] bits in the USART_BRR register, and bit DIV_fraction[3] must be kept cleared.

Note: The baud counters are updated to the new value in the baud registers after a write operation to USART_BRR. Hence the baud rate register value should not be changed during communication.

IrDA low-power mode ……………………….

Transmitter:

In low-power mode the pulse width is not maintained at 3/16 of the bit period. Instead, the width of the pulse is 3 times the low-power baud rate which can be a minimum of 1.42 MHz. Generally this value is 1.8432 MHz (1.42 MHz < PSC< 2.12 MHz). A low-power mode programmable divisor divides the system clock to achieve this value.

Receiver:

Receiving in low-power mode is similar to receiving in normal mode. For glitch detection the USART should discard pulses of duration shorter than 1/PSC. A valid low is accepted only if its duration is greater than 2 periods of the IrDA low-power Baud clock (PSC value in USART_GTPR).

.. image:: /irda.PNG

.. image:: /normal_mode.PNG

USART SYNCHRONOUS MODE …………………. The synchronous mode is selected by writing the CLKEN bit in the USART_CR2 register to

1. In synchronous mode, the following bits must be kept cleared:

● LINEN bit in the USART_CR2 register,

● SCEN, HDSEL and IREN bits in the USART_CR3 register.

The SCLK pin works in conjunction with the TX pin. Thus, the clock is provided only if the transmitter is enabled (TE=1) and a data is being transmitted (the data register USART_DR has been written). This means that it is not possible to receive a synchronous data without transmitting data.

The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. These bits should not be changed while the transmitter or the receiver is enabled.

.. image:: /synchronous_transmission.png

HARDWARE FLOW CONTROL …………………. It is possible to control the serial data flow between 2 devices by using the nCTS input and the nRTS output.

.. image:: /hardware_control_2usarts.png

RTS Flow Control

If the RTS flow control is enabled (RTSE=1), then nRTS is asserted (tied low) as long as the USART receiver is ready to receive a new data. When the receive register is full, nRTS is deasserted, indicating that the transmission is expected to stop at the end of the current frame.

.. image:: /rst_flow_control.png

CTS Flow Control

If the CTS flow control is enabled (CTSE=1), then the transmitter checks the nCTS input before transmitting the next frame. If nCTS is asserted (tied low), then the next data is transmitted (assuming that a data is to be transmitted, in other words, if TXE=0), else the transmission does not occur. When nCTS is deasserted during a transmission, the current transmission is completed before the transmitter stops.

When CTSE=1, the CTSIF status bit is automatically set by hardware as soon as the nCTS input toggles. It indicates when the receiver becomes ready or not ready for communication. An interrupt is generated if the CTSIE bit in the USART_CR3 register is set. The figure below shows an example of communication with CTS flow control enabled.

.. image:: /cst_flow_control.png

PARITY CONTROL ………….. Parity control (generation of parity bit in transmission and parity checking in reception) can be enabled by setting the PCE bit in the USART_CR1 register. Depending on the frame length defined by the M bit, the possible USART frame formats are as listed in Table 118.

.. image:: /frame_formats.png

Even parity

The parity bit is calculated to obtain an even number of “1s” inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.

E.g.: data=00110101; 4 bits set => parity bit will be 0 if even parity is selected (PS bit in USART_CR1 = 0).

Odd parity

The parity bit is calculated to obtain an odd number of “1s” inside the frame made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.

E.g.: data=00110101; 4 bits set => parity bit will be 1 if odd parity is selected (PS bit in USART_CR1 = 1).

Parity checking in reception

If the parity check fails, the PE flag is set in the USART_SR register and an interrupt is generated if PEIE is set in the USART_CR1 register. The PE flag is cleared by a software sequence (a read from the status register followed by a read or write access to the USART_DR data register).

Parity generation in transmission

If the PCE bit is set in USART_CR1, then the MSB bit of the data written in the data register is transmitted but is changed by the parity bit (even number of “1s” if even parity is selected (PS=0) or an odd number of “1s” if odd parity is selected (PS=1)).

CODE SECTION

Download sample code :

.. code-block:: c

git clone https://github.com/wujiheng/stm32f407.git
cd stm32f407/USART

To compile code

.. code-block:: c

make make flash <– 記得把USB連上去

這裡採用minicom 超級終端機來接收USART字串

.. code-block:: c

sudo apt-get install minicom sudo minicom -s <– 不一定要用root，不過使用者必須要device node 讀寫的權限，-s表進入setup

REFERENCE ……………… - Universal asynchronous receiver/transmitter wikipedia.<http://en.wikipedia.org/wiki/Universal_asynchronous_receiver/transmitter#Special_receiver_conditions>_

• STM32F407xx Reference Manual<http://www.st.com/web/en/resource/technical/document/reference_manual/DM00031020.pdf>_

Q&A ……………….

1.Uart 原理

DTE（Data Terminal Equipment）簡稱數據終端設備；DCE（Data Communications Equipment）簡稱數據通信設備。 事實上，RS-232C標準的正規名稱是“數據終端設備和數據通信設備之間串行二進制數據交換的接口”。通常，將通信線路終端一側的計算機或終端稱為DTE，而把連接通信線路一側的調製解調器稱為DCE。 RS-232C標準中所提到的“發送”和“接收”，都是站在DTE立場上，而不是站在DCE的立場來定義的。由於在計算機系統中往往是CPU和I/O設備之間傳送信息，兩者都是DTE，因此雙方都能發送接收。 所謂“串行通信”是指DTE和DCE之間使用一根數據信號線（另外需要地線，可能還需要控制線），數據在一根數據信號線上一位一位地進行傳輸，每一位數據都佔據一個固定的時間長度。這種通信方式使用的數據線少，在遠距離通信中可以節約通信成本，當然，其傳輸速度比並行傳輸慢。

2.高速UART及低速UART之應用?

嵌入在ElanSC520微控制器中的高速UART通信的速度可以高達1.1152Mbps，另外 利用計算機軟件技術(EDA技術)和FPGA／CPLD的靈活性可以方便快速地設計高速和低 速的UART。高速的UART可以用在光纖通信上，低速的UART可以用在FPGA／CPLD和單片機的通信上。

3.紅外線高速之應用?

低速紅外線是指其傳輸速率在每秒115.2Kbits者而言，它適用於傳送簡短的訊息、文字或是檔案。有低速紅外線也有高速紅外線（Fast IR），它是指傳輸速率在每秒1或是4Mbits者而言，其他更高傳輸速率則仍在發展中。對於網路解決方案而言，高速紅外線可以說是其基礎，包括檔案傳輸、區域網路連結甚至是多媒體傳輸。