版本 4529e0bca02ed7c4581c2dd0e61fa31b9e9c32e1
Computer Architecture
- Instructor: Jim Huang (黃敬群)
<jserv.tw@gmail.com> - Facebook Group: https://www.facebook.com/groups/system.software2019/
- Policy
- Follow the classes: CS 61C at UC Berkeley, CS152/252: Computer Architecture
- Course grading
- Quiz (20%), Homework (40%), Final Project (40%)
Computer Architecture (Fall 2021)
- Week 1 (Sep 28): Introduction
- Course Introduction
- David Patterson: A New Golden Age for Computer Architecture: History, Challenges and Opportunities / video
- David Patterson: From Mainframe CPUs to Neural-Network TPUs and Open RISC-V / video
- Great Ideas in Computer Architecture, Intro / video
- Number Representation
- Floating Point
- C Memory Management / video
- Week 2 (Oct 5): Quiz + RISC-V
- Quiz1: C programming, bit-wise operations, number representation, floating-point / Solution
- Lab0: Web-based Emulators
- Introduction to RISC-V Assembly language : Arithmetic
- Intro to Assembly Language and RISC-V / video
- Week 3 (Oct 12): RISC-V
- Week 4 (Oct 19): RISC-V
- Announcement:
- Next quiz is scheduled to Oct 26
- Code Review for Homework 1 on Oct 26
- We might be in a physical classroom next week. Please check the latest announcement via email.
- Apple M1 Pro/Max
- More RISC-V Functions / video
- Compiler, Assembler, Linker, Loader / video
- 2020-Quiz2
- Announcement:
- Week 5 (Oct 26): Quiz + Code Review (Room 4201 (1F) at (old) CSIE Building)
- Quiz2: RISC-V assembly and C programming / solution
- Code Review on Homework1: RISC-V Assembly and Instruction Pipeline
- Week 6 (Nov 2): RISC-V Instruction Format + GNU Toolchain + Code Review (Room 4201 (1F) at (old) CSIE Building)
- Next week: digital logic
- Code Review on Homework1: RISC-V Assembly and Instruction Pipeline
- Lab2: RISC-V RV32I[MA] emulator with ELF support
- Assignment: Homework2: RISC-V Toolchain (Due: Nov 15)
- Further reading FPGA design for Software Engineers
- RISC-V Instruction Formats / video
- Week 7 (Nov 9): Digital Systems
- Announcement: New quiz on Nov 16
- Next generation of rv32emu: sysprog21/rv32emu-next
- Combinational Digital Logic / video
- Sequential Digital Logic / video
- 2020-Quiz3
- Week 8 (Nov 16): Datapath and Control
- Announcement: Due to internal problems of HackMD (pictures were not shown), we would take new scoring method to eliminate the impact. Next week, we have an additional quiz dedicated to Combinational and Sequential Digital Logic.
- Quiz3: RISC-V programming and instruction encoding + Digital systems / solution
- RISC-V CPU Datapath, Control Intro / video
- Single-Cycle CPU Control / video
- Week 9 (Nov 23): Pipeline
- Announcement:
- Next quiz is scheduled to Dec 7
- Quiz4: Digital systems / solution
- video: Are Computers Still Getting Faster?
- MIT 6.004 L15: Introduction to Pipelining, L16: Processor Pipelining, L17: Implementing Pipelining
- slides: Introduction to Pipelining
- slides: Pipelined Processors
- note
- Announcement:
- Week 10 (Nov 30): Pipelined Processors
- Announcement:
- Next quiz is scheduled to Dec 7
- Homework3: SoftCPU is out.
- Next week, we will review all the assignments.
- 0 to ASIC
- L16: Processor Pipelining, L17: Implementing Pipelining, L18: Implementing Pipelined Processors / note
- slides: Pipelined Processors
- slides: Pipelined Processors Data and Control Hazards
- RISC-V 5-Stage Pipeline / Hazards / video
- Complex Pipelines, Out-of-Order Issue, Register Renaming
- Lab3: srv32 - RISCV RV32IM Soft CPU
- Assignment: Homework3: SoftCPU (Due: Dec 20, 2021)
- 2020 Quiz4
- Announcement:
- Week 11 (Dec 7): Quiz + Homework Review
- Week 12 (Dec 14): Cache + Virtual Memory
- Announcement: Quiz on Dec 21 - pipeline, cache and virtual memory
- Caches: Direct-mapped, set-associative / video
- Multi-level Caches, Cache Questions / video
- The golden age of ever-changing computer architecture
- Cerebras announced a system which connects multiple integrated circuits (commonly called “chips”) into a neural network with many connections in Aug 2021. It enables a single system to support AI models with more than 120 trillion parameters.
- Virtual Memory / video
- UCB: Virtual Memory / video
- 2020-Quiz5 / solution
- Week13 (Dec 21): Quiz + Virtual Memory + Operating System
- Announcement:
- Be aware of term projects.
- Next week, we will review all the assignments.
- Quiz6: pipelined processor + cache + virtual memory / solution
- Virtual Memory / video
- Lab4: Cache
- Operating Systems / video
- Term projects 2020
- Announcement:
- Week14 (Dec 28): Synchronization
- Announcement:
- Quiz on Jan 11
- Your grades will be delivered on Jan 21, 2022
- Check the listing of final/term projects
- Term projects 2021
- Synchronization / video
- Thread-Level Parallelism / video
- Let’s skip OpenMP part
- Announcement:
- Week15 (Jan 4): Operating System and RISC-V, cache coherence
- Announcement:
- Quiz7 on Jan 11
- Check the listing of final/term projects
- video: The Future of Operating Systems on RISC-V / transcript
- Multithreading Issues, Cache Coherency / video
- Let’s skip OpenMP part
- Freestanding RISC-V Programs
- Multithreaded Application Synchronization Part I
- Multithreaded Application Synchronization Part II
- RISC-V AMOSWAP instruction
- Advanced topics on Synchronization - 1
- Advanced topics on Synchronization - 2
- 2020 Quiz6
- Announcement:
- Week16 (Jan 11): I/O
- Quiz7 / solution
- I/O: Devices, Polling, Interrupts / video
- Traps/Interrupts/Exceptions
- Trap Handling in 5-Stage Pipeline
- Week17 (Jan 18): Modern Processors
Computer Architecture (Fall 2020)
Week 1
- David Patterson: A New Golden Age for Computer Architecture: History, Challenges and Opportunities / video
- David Patterson: From Mainframe CPUs to Neural-Network TPUs and Open RISC-V / video
- Great Ideas in Computer Architecture, Intro / video
- Number Representation
- Floating Point
- C Memory Management / video
Week 2: Quiz + RISC-V
- Quiz1: C programming, bit-wise operations, number representation, floating-point / Solution
- News: NVIDIA to Acquire Arm for $40 Billion, Creating World’s Premier Computing Company for the Age of AI
- Lab0: Web-based Emulators
- Introduction to RISC-V Assembly language : Arithmetic
- Intro to Assembly Language and RISC-V / video
Week 3: RISC-V
Week 4: RISC-V
- Announcement:
- quiz rescheduled to Oct 6
- Code Review for Homework 1 on Oct 6
- More RISC-V Functions / video
- Compiler, Assembler, Linker, Loader / video
- Announcement:
Week 5: Quiz + Code Review
- Quiz2
- Code Review on Homework1: RISC-V Assembly and Instruction Pipeline
Week 6: RISC-V and Toolchain
- Collaborative notes
- Next week: digital logic
- Code Review on Homework1: RISC-V Assembly and Instruction Pipeline
- Lab2: RISC-V RV32I[MA] emulator with ELF support
- Assignment: Homework2: RISC-V Toolchain (Due: Oct 26)
- Further reading FPGA design for Software Engineers
- RISC-V Instruction Formats / video
Week 7: Digital Systems
- nand2tetris / TED Talk
- Next generation of rv32emu: sysprog21/rv32emu-next
- Combinational Digital Logic / video
- Sequential Digital Logic / video
Week 8: Datapath
- Quiz3
- Lab3: Reindeer - RISCV RV32I[M] Soft CPU
- RISC-V CPU Datapath, Control Intro / video
- Assignment: Homework3: SoftCPU (Due: Nov 16)
Week 9: Control, Pipeline
- Collaborative notes
- Announcement: quiz4 on Nov17: CPU datapath, control, pipeline
- video: Are Computers Still Getting Faster?
- Single-Cycle CPU Control / video
- MIT 6.004 L15: Introduction to Pipelining, L16: Processor Pipelining, L17: Implementing Pipelining
Week 10: Pipelined Processors
Week 11: Quiz + Homework Review
Week 12: Cache + Virtual Memory
- Announcement: Quiz on Dec 1 - pipeline, cache and virtual memory
- Caches: Direct-mapped, set-associative / video
- Multi-level Caches, Cache Questions / video
- The golden age of ever-changing computer architecture
- Virtual Memory / video
Week13: Quiz + Virtual Memory
- Quiz5
- Virtual Memory / video
- Term projects 2019
- Implement RISC-V Compressed Instruction Set on rv32emu
- Implement RISC-V Compressed Instruction Set for Reindeer, based on pull request RV32C support. must be validated on Step CYC10 FPGA board.
- Contribute to Ripes: pick up pending issues, work on them, and finally send pull request(s).
- Prepare practical tutorials for VSRTL, thus people can follow the instructions for implementing minimal RISC-V core such as minrv32.
- Analyze spu32 with Yosys open synthesis suite. Explain how it works and validate it.
- Analyze VexRiscv. Explain how it works and validate it.
- Modify Reindeer to allow non-trial interactive games on Step CYC10 FPGA board, based on Reindeer_Step and Zephyr RTOS.
- Lab4: Cache
Week14: Synchronization
- Announcement: Quiz on Dec 22
- Assignment: Homework4: Cache (Due: Dec 26)
- Operating Systems / video
- Synchronization / video
- Thread-Level Parallelism / video
Week15: Operating System and RISC-V
- Term projects 2020
- You must provide the materials and demonstrate to the lecturer before Jan 19, 2021
- video: The Future of Operating Systems on RISC-V / transcript
- Advanced topics on Synchronization - 1
- Advanced topics on Synchronization - 2
- Term projects 2020
Week16: I/O, cache coherence
- Term projects 2020
- You must provide the materials and demonstrate to the lecturer before Jan 19, 2021
- Quiz6
- I/O: Devices, Polling, Interrupts / video
- Traps/Interrupts/Exceptions
- Trap Handling in 5-Stage Pipeline
- Multithreading Issues, Cache Coherency / video
- Cache Coherence / video
- Modern microprocessors usually have 2 to 8 cores where each core has a private cache for performance
- Modified/Shared/Invalid (MSI) Protocol, MESI: An Enhanced MSI protocol to increased performance for private read-write data
- Term projects 2020
Week17: class will be suspended
Week18
Computer Architecture (Fall 2019)
Week 1 (Sep 12)
Week 2 (Sep 19): Quiz
Week 3 (Sep 26): Suspension
Week 4 (Oct 3): RISC-V
Week 5 (Oct 10): Holiday
Week 6 (Oct 17): RISC-V and Toolchain
- Lab2: RISC-V RV32I[MA] emulator with ELF support
- RISC-V Instruction Formats I / video
- Compilation, Assembly, Linking, Loading
- Assignment: Homework2: RISC-V Toolchain (Due: Oct 30, 2019)
- Further reading FPGA design for Software Engineers
Week 7 (Oct 24): RISC-V and Digital Systems
- ANN: Next week, we will have another quiz.
- RISC-V Procedures
- Practice: RISC-V Control Flow, CALL, RISC-V Procedures
- Practice: CS 152 Computer Architecture and Engineering - Midterm #1
- Problem 2: Microcoding: writing microcode for a bus-based implementation of the RISC-V machine
- Problem 3: 5-Stage Pipelines
- Intro to Synchronous Digital Systems / video
- State
- Combinational Logic
- Combinational Logic Blocks / video
- Practice: Logic
Week 8 (Oct 31): Datapath
- Lab3: Reindeer - RISCV RV32I[M] Soft CPU
- Single-Cycle CPU Datapath I
- Single-Cycle CPU Datapath II
- Single-Cycle CPU Control / video
- Quiz
- Assignment: Homework3: SoftCPU (Due: Nov 20, 2019)
Week 9 (Nov 7): Pipeline
Week 10 (Nov 14): Pipelined Proccesors
Week 11 (Nov 21): Cache
Week 12 (Nov 28): Virtual Memory
Week13 (Dec 5): State-of-the-Art mobile computing & Synchronization
- Processors in 5G era: Cortex-A77 + Cortex-A55
- The Race to Exascale at Supercomputer 2019
- Term projects (due date: Jan 5, 2020)
- explore the workings of virtual memory, specifically the TLB and the Page Table
- Implement RISC-V Compressed Instruction Set on rv32emu
- Implement RISC-V Compressed Instruction Set for Reindeer, based on pull request RV32C support. must be validated on Step CYC10 FPGA board.
- Contribute to Ripes: pick up pending issues, work on them, and finally send pull request(s).
- Prepare practical tutorials for VSRTL, thus people can follow the instructions for implementing minimal RISC-V core such as minrv32.
- Analyze spu32 with Yosys open synthesis suite. Explain how it works and validate it.
- Analyze VexRiscv. Explain how it works and validate it.
- Modify Reindeer to allow non-trial interactive games on Step CYC10 FPGA board, based on Reindeer_Step and Zephyr RTOS.
- Synchronization / video
Week14 (Dec 12): Synchronization
Week15 (Dec 19): I/O and Cache Coherence
- Announce: Last quiz on Dec 26, Review final project on Jan 2
- I/O: Devices, Polling, Interrupts / video
- Traps/Interrupts/Exceptions
- Trap Handling in 5-Stage Pipeline
- Cache Coherence / video
- Modern microprocessors usually have 2 to 8 cores where each core has a private cache for performance
- Modified/Shared/Invalid (MSI) Protocol, MESI: An Enhanced MSI protocol to increased performance for private read-write data
- Modern Processor Architecture / video
Week16 (Dec 26): Review and Branch Prediction
Week17 (Jan 2): Term Project Review
