版本 7a0d33b753731e263ce8a8831b115ee3b799d131
Computer Architecture
- Instructor: Jim Huang (黃敬群)
<jserv.tw@gmail.com> - Facebook Group: https://www.facebook.com/groups/system.software2019/
- Policy
- Follow the classes: CS 61C at UC Berkeley, CS152/252: Computer Architecture
- Course grading
- Quiz (20%), Homework (40%), Final Project (40%)
Computer Architecture (Fall 2019)
Week 1 (Sep 12)
Week 2 (Sep 19): Quiz
Week 3 (Sep 26): Suspension
Week 4 (Oct 3): RISC-V
Week 5 (Oct 10): Holiday
Week 6 (Oct 17): RISC-V and Toolchain
- Lab2: RISC-V RV32I[MA] emulator with ELF support
- RISC-V Instruction Formats I / video
- Compilation, Assembly, Linking, Loading
- Assignment: Homework2: RISC-V Toolchain (Due: Oct 30, 2019)
- Further reading FPGA design for Software Engineers
Week 7 (Oct 24): RISC-V and Digital Systems
- ANN: Next week, we will have another quiz.
- RISC-V Procedures
- Practice: RISC-V Control Flow, CALL, RISC-V Procedures
- Practice: CS 152 Computer Architecture and Engineering - Midterm #1
- Problem 2: Microcoding: writing microcode for a bus-based implementation of the RISC-V machine
- Problem 3: 5-Stage Pipelines
- Intro to Synchronous Digital Systems / video
- State
- Combinational Logic
- Combinational Logic Blocks / video
- Practice: Logic
Week 8 (Oct 31): Datapath
- Lab3: Reindeer - RISCV RV32I[M] Soft CPU
- Single-Cycle CPU Datapath I
- Single-Cycle CPU Datapath II
- Single-Cycle CPU Control / video
- Quiz
- Assignment: Homework3: SoftCPU (Due: Nov 20, 2019)
Week 9 (Nov 7): Pipeline
Week 10 (Nov 14): Pipelined Proccesors
Week 11 (Nov 21): Cache
Week 12 (Nov 28): Virtual Memory
Week13 (Dec 5): State-of-the-Art mobile computing & Synchronization
- Processors in 5G era: Cortex-A77 + Cortex-A55
- The Race to Exascale at Supercomputer 2019
- Term projects (due date: Jan 5, 2020)
- explore the workings of virtual memory, specifically the TLB and the Page Table
- Implement RISC-V Compressed Instruction Set on rv32emu
- Implement RISC-V Compressed Instruction Set for Reindeer, based on pull request RV32C support. must be validated on Step CYC10 FPGA board.
- Contribute to Ripes: pick up pending issues, work on them, and finally send pull request(s).
- Prepare practical tutorials for VSRTL, thus people can follow the instructions for implementing minimal RISC-V core such as minrv32.
- Analyze spu32 with Yosys open synthesis suite. Explain how it works and validate it.
- Analyze VexRiscv. Explain how it works and validate it.
- Modify Reindeer to allow non-trial interactive games on Step CYC10 FPGA board, based on Reindeer_Step and Zephyr RTOS.
- Synchronization / video
Week14 (Dec 12): Synchronization
Week15 (Dec 19): I/O and Cache Coherence
- Announce: Last quiz on Dec 26, Review final project on Jan 2
- I/O: Devices, Polling, Interrupts / video
- Traps/Interrupts/Exceptions
- Trap Handling in 5-Stage Pipeline
- Cache Coherence / video
- Modern microprocessors usually have 2 to 8 cores where each core has a private cache for performance
- Modified/Shared/Invalid (MSI) Protocol, MESI: An Enhanced MSI protocol to increased performance for private read-write data
- Modern Processor Architecture / video
Week16 (Dec 26): Review and Branch Prediction
Week17 (Jan 2): Term Project Review
