版本 1316a64efce8d1dece7fc093e4cf1dd218b53156

Computer Architecture

Instructor: Jim Huang (黃敬群) <jserv.tw@gmail.com>
Facebook Group: https://www.facebook.com/groups/system.software2024/
Policy
- Follow the classes: CS 61C at UC Berkeley, CMU 18-447: Introduction to Computer Architecture
Course grading
- Quiz (30%), Homework (30%), Final/Term Project (40%)
Schedule is tentative and subject to change!

Computer Architecture (Fall 2024)

Week 1 (Sep 10): Introduction
- Announcement
  - Despite September 17th being a national holiday for Mid-Autumn Festival, our class will continue as scheduled, and students are required to complete an online quiz. For information on how to participate and access the remote class, please refer to this website.
- Course Introduction
- David Patterson: A New Golden Age for Computer Architecture: History, Challenges and Opportunities / video
  - Article, note
- David Patterson: From Mainframe CPUs to Neural-Network TPUs and Open RISC-V / video
- Great Ideas in Computer Architecture / video
- Number Representation / video
- Understanding Floating Point Struggles / Floating Point (video)
- C Memory Management / video
- RISC-V Instructions
Week 2 (Sep 17): Quiz
- Announcement
  - The first assignment, consisting of RISC-V assembly programming, will be given next week.
- Quiz1: C programming, bit-wise operations, number representation, floating-point / Solutions
Week 3 (Sep 24): RISC-V
- Announcement:
  - Quiz2 is scheduled on Oct 1: Due to the possibility that the classroom capacity may not accommodate the number of enrolled students, additional classrooms may be arranged as test venues. Please make sure to check this page on the evening of September 30th for related announcements.
    - 2023 Quiz2: RISC-V assembly and C programming / solution
    - 2022 Quiz2: RISC-V assembly and C programming / solution
    - 2021 Quiz2: RISC-V assembly and C programming / solution
  - Homework 1 is out.
  - Code Review for Homework 1 on Oct 8
- Principles of this course
- Intro to RISC-V / video
  - RISC-V Assembly Programmer’s Manual
  - The RISC-V Instruction Set Manual: Volume I: Unprivileged ISA
- RISC-V Data Transfer / video
- RISC-V Decision Making and Logical Operations / video
- RISC-V Procedures / video
- Lab0: Web-based Emulators
- Lab1: RV32I Assembly
- Assignment: Homework1: RISC-V Assembly and Instruction Pipeline (Due: Oct 14, 2024)
Week 4 (Oct 1): Quiz + RISC-V
- Announcement
  - Due to the impact of Typhoon Krathon, Quiz 2 will be conducted online instead of in-person. Please refresh this web page to obtain the latest information on how to participate in the online quiz and attend the course remotely.
  - Access the live-streamed course on YouTube. Watch the live stream carefully: Quiz 2 participation instructions will be provided during the broadcast.
- Quiz2: RISC-V assembly and C programming / solution
- Fixed-point Arithmetic
- RISC-V Instruction Formats Part I / video
- RISC-V Instruction Formats Part II / video
Week 5 (Oct 8): RV32I + Code Review
- Review: RISC-V Architecture Instruction Encoding
  - Revisit the RV32I specification and instruction encoding, as they serve as the foundation for implementing RISC-V processor cores in HDL.
  - The system instructions: ecall, ebreak, and csr*.
  - online tool for RISC-V Instruction Encoder/Decoder / source code
- Recursion as a Problem-Solving Technique
- Code Review on Homework1: RISC-V Assembly and Instruction Pipeline
Week 6 (Oct 15): Toolchain + Digital Systems
- Announcement
  - Quiz 3 is scheduled for Oct 22 and will cover RISC-V assembly programming, software optimizations, instruction encoding, sequential logic, and combinational logic.
    - 2020-Quiz3 / solution
    - 2021-Quiz3 / solution
    - 2021-Quiz4 / solution
    - 2022-Quiz3 / solution
    - 2023-Quiz3 / solution
- Compiling, Assembling, Linking, and Loading / video-1 + video-2
- Lab2: RISC-V + VENUS / slides
- Binary marble adding machine / video
  - Yes, you can implement a few logic-like elements without electricity.
  - Logic gates are primarily implemented using diodes or transistors acting as electronic switches, but can also be constructed using vacuum tubes, electromagnetic relays (relay logic), fluidic logic, pneumatic logic, optics, molecules, or even mechanical elements. Now, most logic gates are made from MOSFETs (metal–oxide–semiconductor field-effect transistors).
- Synchronous Digital Systems (SDS) / video
- Combinational Logic / video
  - sequential logic is a type of logic circuit whose output depends on the present value of its input signals and on the sequence of past inputs, the input history.
- SDS State / video
- Combinational Logic Blocks / video
Week 7 (Oct 22): Quiz
- Quiz3: RISC-V programming and instruction encoding + Digital systems / solution
Week 8 (Oct 29): Review + Datapath and Control
- Announcement:
  - Homework 2 is undergoing significant revisions. Please keep an eye on your email for updates.
  - The instructor has been grappling with the LLM for several weeks though.
- “What I cannot create, I do not understand.” - On Richard Feynman’s blackboard at the time of his death in 1988 / Build Your Own X
- Revisit Quiz 3
  - RISC-V Architecture Instruction Encoding
  - World’s Fastest Square Root: Newton’s Method
- RISC-V Datapath I / video
Week 9 (Nov 5): Datapath and Control + Pipeline
- Announcement:
  - Homework 2 is out. Deadline: Nov 18, 2024
- video: Are Computers Still Getting Faster?
- video: Circuits recap
- RISC-V Datapath II / video
- RISC-V Processor Design Control / video
- Constructing Hardware in a Scala Embedded Language (Chisel) is an open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs.
  - slides
  - Finite impulse response (FIR)
  - Learn Chisel online!
    - Please run the cell blocks by either pressing SHIFT+ENTER on your keyboard
- MIT 6.191 L15: Introduction to Pipelining, L16: Processor Pipelining
  - note
Week 10 (Nov 12): Pipelined Processors
- Announcement:
  - Next week, we will continue reviewing all the assignments.
  - Quiz 4 is scheduled next week.
    - 2020 Quiz4 / solution
    - 2021 Quiz5 / solution / annotated with Ripes
    - 2022 Quiz4 / solution / annotated
    - 2023 Quiz4 / solution / annotated
  - The next homework assignment will be given out next week, along with Quiz 4. Please review last year’s homework to get familiar with the procedure and expectations.
- rv32emu development, capable of running Linux kernel smoothly (#508)
- 0 to ASIC
- L16: Processor Pipelining, L17: Implementing Pipelining, L18: Implementing Pipelined Processors / note
- RISC-V 5-Stage Pipeline / video-1, video-2, video-3
- Lab3: Construct a single-cycle CPU with Chisel
Week 11 (Nov 19): Quiz + Homework Review
- Quiz4: RISC-V programming + datapath + control + pipelined processor / solution
- Homework1, Homework2
Week 12 (Nov 26): Cache
- Announcement
  - Moved to self-study, no in-class session today!
- Cache (1) / video
- Cache (2) / video
- Cache (3) / video
- Cache (4) / video
- Recall: The golden age of ever-changing computer architecture
  - The next big tech war front: RISC-V
  - Designing in 2023: 10 Problems to Solve - Jim Keller, Tenstorrent
    - Oral History of Jim Keller
Week13 (Dec 3): Virtual Memory + Operating System + Vector Extension
- Announcement:
  - Quiz 5 is scheduled on Dec 10
    - 2023-Quiz5 / solution / annotated
    - 2022-Quiz5 / solution / annotated
    - 2021-Quiz6 / solution / with Ripes simulation
    - 2020-Quiz5 / solution
  - This semester, we will conduct 7 quizzes. Out of these, the best 4 will be selected for grading purposes.
  - The instructor will submit the grades on the school’s designated deadline (Jan 24, 2025) for grade registration. This means that students will have ample time to dedicate to the final project assigned in this course.
  - Term projects will be listed on Dec 5. Term projects of 2023
- News: Intel Announces Retirement of CEO Pat Gelsinger - Early last month, Intel was removed from the Dow Jones Industrial Average, which comprises 30 leading U.S. stocks, to make room for Nvidia as the index shifts toward AI pioneers. / What Is the Dow Jones Industrial Average?
- Lab3: Construct a RISC-V CPU with Chisel
- Virtual Memory
  - UCB: Virtual Memory I / video
  - UCB: Virtual Memory II / video
- The Future of Mission Critical Edge Compute Is RISC-V
  - (12:47) multi-core flexibility: SMP, AMP, hypervisor
  - Lockstep systems are fault-tolerant computers that simultaneously perform identical operations in parallel. Borrowed from military marching terminology, these systems use redundancy to detect and correct errors. With two systems (dual modular redundancy), errors can be identified, and with three systems (triple modular redundancy), errors can be automatically corrected through majority voting.
  - Customizing Linux Systems in Aerospace
- Freestanding RISC-V Programs
  - bare metal
- UCB: Operating Systems
- RISC-V Vector extension (RVV)
Week14 (Dec 10): Quiz + Synchronization
- Announcement:
  - Regarding the final project, students may form groups of 1 to 3 members (the project’s difficulty will depend on the group size and members’ backgrounds). Please refer to last year’s projects for reference and send an email to jserv.tw@gmail.com, specifying your group members and proposed project topics (you may suggest multiple topics, with the final decision made by the instructor).
  - Check the listing of final/term projects in 2023 for reference.
- Quiz5: pipelined processor + cache + virtual memory / solution
- Debunking CISC vs RISC code density
- Synchronization
  - Please check your operating system textbook for such topic.
Week15 (Dec 17): Operating System, Multithreading
- Announcement:
  - Quiz6 is scheduled on Dec 24
    - 2023-Quiz6 / solution
    - 2022-Quiz6 / solution
    - 2021-Quiz7 / solution
    - 2021-Quiz6 / solution
    - 2020-Quiz6 / solution
  - Term Projects: You must provide the materials and demonstrate to the lecturer before Jan 23, 2025
- Synchronization
  - Please check your operating system textbook for such topic.
- Multithreading Issues + Cache Coherency
  - Let’s skip OpenMP part
- video: The Future of Operating Systems on RISC-V / transcript
- Multithreaded Application Synchronization Part I / Part II
  - Taken from CSCI 463: Computer Architecture and Systems Organization
  - RISC-V AMOSWAP instruction
  - RISC-V spec references the word ‘hart’ - what does ‘hart’ mean?
Week16 (Dec 24): Quiz + Memory Model, I/O
- Announcement:
  - The class will be held online next week. (Happy New Year!) Please check this page for updates.
  - Quiz7 is scheduled on Jan 7, 2025.
  - The term projects will be reviewed on Jan 7.
- Quiz6 / solution
- Memory Model / slides
- I/O: Devices, Polling, Interrupts / video
  - Traps/Interrupts/Exceptions
  - Trap Handling in 5-Stage Pipeline
Week17 (Dec 31): Modern Processors
- Announcements
  - Quiz7 is scheduled on Jan 7, 2025
- rv32emu introduces tier-1 JIT compiler to accelerate RISC-V simulation.
  - Execute make ENABLE_JIT=1 clean all and then run build/rv32emu build/smolnes.elf to play NES games.
- Modern Processor Architecture
  - Modern Microprocessors: A 90-Minute Guide!
- Introduction to Dynamic Branch Prediction, Advanced Branch Prediction
Week 18 (Jan 7): Modern Processors
- Quiz7 / solution
- Tournament Predictors and Branch Prediction Accuracy
- Project: Analyze and improve srv32
- Hardware Based Speculation
  - Speculative Processor Vulnerability
  - Spectre-BHB
- Case study: SoomRV - simple superscalar out-of-order RISC-V core. It can execute up to 4 instructions per cycle and is able to boot Linux.
- RISC vs. CISC by John Mashey, one of the founders of the Standard Performance Evaluation Corporation (SPEC) benchmarking group.
  - HackerNews