Computer Architecture

• Instructor: Jim Huang (黃敬群) <jserv.tw@gmail.com>
• Facebook Group: https://www.facebook.com/groups/system.software2023/
• Policy
  • Follow the classes: CS 61C at UC Berkeley, CS152/252: Computer Architecture
• Course grading
  • Quiz (30%), Homework (30%), Final/Term Project (40%)
• Schedule is tentative and subject to change!

Computer Architecture (Fall 2023)

• Week 1 (Sep 5): Introduction

  • Course Introduction
  • David Patterson: A New Golden Age for Computer Architecture: History, Challenges and Opportunities / video
    • Article, note
  • David Patterson: From Mainframe CPUs to Neural-Network TPUs and Open RISC-V / video
  • Great Ideas in Computer Architecture, Intro / video
  • Number Representation / video
  • Floating Point / video
  • C Memory Management / video

• Week 2 (Sep 12): Quiz + RISC-V / online via YouTube

  • Announcement
    • There is an online quiz from 10:50 AM to 11:59 AM.
    • The first assignment, consisting of RISC-V assembly programming, will be given next week.
  • Quiz1: C programming, bit-wise operations, number representation, floating-point / Solutions
  • RISC-V Instructions

• Week 3 (Sep 19): RISC-V

  • Announcement:
    • Quiz2 is scheduled on Sep 26
      • 2022 Quiz2: RISC-V assembly and C programming / solution
      • 2021 Quiz2: RISC-V assembly and C programming / solution
    • Homework 1 is out.
    • Code Review for Homework 1 on Oct 3
  • Apple A17 Pro
    • 19 billion transistors compared to 16 billion on the A16. further reading
    • graphics benchmark
    • ARM1 (1985) vs. Apple M1 Max (2021)
    • Apple Announces M1 Pro & M1 Max: Giant New Arm SoCs with All-Out Performance
  • RISC-V Summit China 2023 / slides
  • Intro to Assembly Language and RISC-V / video
    • RISC-V Assembly Programmer’s Manual
    • The RISC-V Instruction Set Manual: Volume I: Unprivileged ISA
  • RISC-V Data Transfer / video
  • RISC-V Decision Making
  • Functions Calls with RISC-V / video
  • Lab0: Web-based Emulators
  • Lab1: RV32I Assembly
  • Assignment: Homework1: RISC-V Assembly and Instruction Pipeline (Due: Oct 10, 2023)

• Week 4 (Sep 26): Quiz + RISC-V

  • Errata
    • 2023 Quiz1: Additional x += (x >> 32) statement in Problem A
  • Quiz2: RISC-V assembly and C programming / solution
  • Fixed-point Arithmetic
  • NASA, Microchip, SiFive Announces Partnership for RISC-V Spaceflight Computing Platform
  • ST, CAES team on octacore RISC-V space chip with selectable cores
  • Calling Convention for RISC-V / video
  • CALL = Compiling, Assembling, Linking, and Loading / video

• Week 5 (Oct 3): Code Review + RISC-V Instruction Format + GNU Toolchain

  • Announcement
    • On October 10th, we will be conducting a makeup lesson for the Computer Architecture course. Please visit this website for online class information (recording included).
    • Homework2: RISC-V Toolchain is out.
  • Code Review on Homework1: RISC-V Assembly and Instruction Pipeline
  • Lab2: RISC-V RV32I[MACF] emulator with ELF support
  • Assignment: Homework2: RISC-V Toolchain (Due: Oct 31)
  • RISC-V Instruction Formats Part I / Part II / video

• Week 6 (Oct 10): National Day | make up a lesson on Oct 12 night via YouTube

  • Announcement: Given the consistent progress of the lecture, we will schedule a makeup lesson for 19:30 on October 12th via YouTube.
  • RISC-V Instruction Formats Part I / Part II / video
    • online tool for RISC-V Instruction Encoder/Decoder / source code
  • Further reading FPGA design for Software Engineers

• Week 7 (Oct 17): Digital Systems

  • Binary marble adding machine / video
    • Yes, you can implement a few logic-like elements without electricity.
    • Logic gates are primarily implemented using diodes or transistors acting as electronic switches, but can also be constructed using vacuum tubes, electromagnetic relays (relay logic), fluidic logic, pneumatic logic, optics, molecules, or even mechanical elements. Now, most logic gates are made from MOSFETs (metal–oxide–semiconductor field-effect transistors).
  • nand2tetris
  • Synchronous Digital Systems (SDS), Boolean Algebra / video
    • sequential logic is a type of logic circuit whose output depends on the present value of its input signals and on the sequence of past inputs, the input history.
  • State, Combinational Logic / video
  • 2020-Quiz3 / solution
  • 2021-Quiz3 / solution
  • 2021-Quiz4 / solution

• Week 8 (Oct 24): Datapath and Control + Code Review

  • Quiz3: RISC-V programming and instruction encoding + Digital systems / solution
  • RISC-V CPU Datapath / video

• Week 9 (Oct 31): Pipeline

  • video: Are Computers Still Getting Faster?
  • video: Circuits recap
  • RISC-V CPU Datapath / video
    • slides
  • Single-Cycle CPU Control / video
    • slides
  • MIT 6.191 L15: Introduction to Pipelining, L16: Processor Pipelining
    • note

• Week 10 (Nov 7): Pipelined Processors

  • Announcement:
    • Homework3 SoftCPU is out.
    • Next week, we will review all the assignments.
  • Recent rv32emu changes
    • More descriptions about system calls. See docs/syscall.md
    • Implement clock_gettime system call, so that you can call gettimeofday/clock_gettime in C programs.
    • Implement user-level counters for getting CPU cycle counts in RISC-V programs. See tests/perfcounter for sample usage.
    • Better experiences while running Doom and Quake games. You can resize the window and use mouse properly.
    • More test programs: jit-bf (JIT assembler for RISC-V), coro (a simple coroutine implementation for RISC-V), mandelbrot (an ASCII-based renderer for Mandelbrot Set, colorized), richards (an operating system task scheduler simulation benchmark), and chacha20 (stream cipher)
    • More comments in source files.
  • 0 to ASIC
  • L16: Processor Pipelining, L17: Implementing Pipelining, L18: Implementing Pipelined Processors / note
  • RISC-V 5-Stage Pipeline / Hazards / video
  • Lab3: srv32 - RISCV RV32IM Soft CPU
  • Assignment: Homework3: SoftCPU (Due: Nov 30, 2022)
  • 2020 Quiz4 / solution
  • 2021 Quiz5 / solution / annotated with Ripes

• Week 11 (Nov 14): Quiz + Homework Review (Room 4201 (1F) at (old) CSIE Building)

  • Quiz4: RISC-V programming + datapath + control + pipelined processor / solution
  • Homework1, Homework2
  • Complex Pipelines, Out-of-Order Issue, Register Renaming

• Week 12 (Nov 21): Cache + Virtual Memory

  • Announcement
    • Term projects will be listed on Nov 29
  • Caches: Direct-mapped, set-associative / video
  • Multi-level Caches, Cache Questions / video
  • The golden age of ever-changing computer architecture
    • Computing on Andromeda: Chip Company Releases 13.5M Core Supercomputer
    • Designing in 2023: 10 Problems to Solve w/ Jim Keller - Tenstorrent 8-wide Ascalon RISC-V core.
  • Virtual Memory / UCB: Virtual Memory / video
  • 2021-Qui6 / solution / with Ripes simulation
  • 2020-Quiz5 / solution

• Week13 (Nov 28): Quiz + Virtual Memory + Operating System (Room 4201 (1F) at (old) CSIE Building)

  • Announcement:
    • Be aware of Term projects
  • Quiz5: pipelined processor + cache + virtual memory / solution
  • Virtual Memory / video
  • Lab4: Cache
    • Reference work
  • Operating Systems / video

• Week14 (Dec 5): Synchronization

  • Announcement:
    • Check the listing of final/term projects and fill in your names.
  • Apple Silicon Guide
  • Debunking CISC vs RISC code density
  • Operating Systems / video
  • Synchronization
    • Please check your operating system textbook for such topic.
  • Thread-Level Parallelism / video
    • Let’s skip OpenMP part
  • Multithreading Issues + Cache Coherency / video
  • 2021 Quiz7 /solution
  • 2021 Quiz6 /solution
  • 2020 Quiz6 /solution

• Week15 (Dec 12): suspended

• Week16 (Dec 19): Multithreading, Synchronization, I/O

  • Quiz6 / solution
  • video: The Future of Operating Systems on RISC-V / transcript
  • Freestanding RISC-V Programs
    • bare metal
  • Multithreaded Application Synchronization Part I
    • Taken from CSCI 463: Computer Architecture and Systems Organization
    • RISC-V spec references the word ‘hart’ - what does ‘hart’ mean?
  • Multithreaded Application Synchronization Part II
    • RISC-V AMOSWAP instruction
  • Advanced topics on Synchronization - 1
  • Advanced topics on Synchronization - 2
  • I/O: Devices, Polling, Interrupts / video
    • Traps/Interrupts/Exceptions
    • Trap Handling in 5-Stage Pipeline

• Week17 (Dec 26): Modern Processors

  • Quiz7 / solution
  • listing of final/term projects
    • You must provide the materials and demonstrate to the lecturer before Jan 13, 2023.
    • Summarize what you did and send email to <jserv.tw@gmail.com>.
  • Modern Processor Architecture
  • Introduction to Dynamic Branch Prediction, Advanced Branch Prediction, Tournament Predictors and Branch Prediction Accuracy
  • Project: Analyze and improve srv32
  • Hardware Based Speculation

• Week 18 (Jan 2): Modern Processors

  • Modern Processor Architecture
  • Introduction to Dynamic Branch Prediction, Advanced Branch Prediction, Tournament Predictors and Branch Prediction Accuracy
  • Project: Analyze and improve srv32
  • Hardware Based Speculation
    • Speculative Processor Vulnerability
    • Spectre-BHB
  • Case study: VRoom - very high end RISC-V implementation, cloud server class, out of order, super scalar, speculative, up to 8 IPC
    • slides / List of ARM processors
  • RISC vs. CISC by John Mashey, one of the founders of the Standard Performance Evaluation Corporation (SPEC) benchmarking group.
    • HackerNews