NOTICE: You must participate in at least one post-quiz or homework
oral discussion in person before December 30, 2025; otherwise, no credit
will be awarded for quizzes.
If you voluntarily participate in the class discussions for Quiz1, please email
the instructor afterward, including your responses to the instructor’s
questions and any follow-up contributions. You will receive an
additional 10 points for Quiz 1.
In today’s class, we will discuss the progress of Homework 1
with the students. Whether you are voluntarily or non-voluntarily
participating in the Q&A, you should follow the assignment
guidelines, prepare your HackMD notes, and set them to public.
When the instructor talks with you, you should paste the link to your
HackMD notes for Homework 1
here. \(\to\)2025-10-07
Quiz 3 is scheduled for Oct 21. Be sure to carefully review past
quizzes, understand their level of difficulty, and practice
thoroughly.
Quiz 3 is scheduled for Oct 21 and will cover RISC-V assembly
programming, software optimizations, instruction encoding, sequential
logic, and combinational logic.
The follow-ups for Quizzes 1 and 2, including lecture discussions
and further improvements, have been updated in the syllabus. Please
review them carefully.
Homework 2 will be assigned next week, focusing on bare-metal
programming, an essential skill for embedded system engineers. Search bare-metal
via Google Career.
Yes, you can implement a few logic-like elements without
electricity.
Logic gates are primarily implemented using diodes or transistors
acting as electronic switches, but can also be constructed using vacuum
tubes, electromagnetic relays (relay logic), fluidic logic, pneumatic
logic, optics, molecules, or even mechanical elements. Now, most logic
gates are made from MOSFETs (metal–oxide–semiconductor field-effect
transistors).
sequential logic is a type of logic circuit whose output depends on
the present value of its input signals and on the sequence of past
inputs, the input history.
Quiz3:
RISC-V programming and instruction encoding + Digital systems / solution
Week 8 (Oct 28): Review + Datapath and Control
Announcement:
The textual description of Problem D in Quiz3 is correct,
but the accompanying image is incorrect. As compensation, all
participants of Quiz 3 will receive a 15-point increase.
If you voluntarily participate in the class discussions for Quiz3, please email
the instructor afterward, including your responses to the instructor’s
questions and any follow-up contributions. You will receive an
additional 10 points for Quiz 3.
“What I cannot create, I do not understand.” - On Richard Feynman’s
blackboard at the time of his death in 1988 / Build Your Own X
an interactive tutorial created by dramforever that introduces the
fundamentals of RISC-V assembly programming through hands-on
experimentation. Inspired by Easy 6502, it uses a browser-based
simulator to let learners observe every step of program execution — from
instruction decoding to register and memory state changes — without
requiring any software installation or toolchain setup.
The tutorial focuses on the minimalist yet complete RV32I + Zicsr
instruction set, guiding readers from their first simple instruction
sequence (addi, ebreak) to more complex topics such as arithmetic and
logic operations, branches, jumps, memory access, stack management,
function calls, control and status registers (CSRs), privilege levels,
exceptions, and even the construction of a bare-bones operating
system.
Constructing Hardware in a Scala Embedded Language (Chisel) is an
open-source hardware description language (HDL) used to describe digital
electronics and circuits at the register-transfer level that facilitates
advanced circuit generation and design reuse for both ASIC and FPGA
digital logic designs.
This semester, we will conduct 7 quizzes. Out of these, the best 4
will be selected for grading purposes.
The instructor will submit the grades on the school’s designated
deadline (Jan 24,
2025) for grade registration. This means that students will have
ample time to dedicate to the final project assigned in this
course.
Lockstep
systems are fault-tolerant computers that simultaneously perform
identical operations in parallel. Borrowed from military marching
terminology, these systems use redundancy to detect and correct errors.
With two systems (dual modular redundancy), errors can be identified,
and with three systems (triple modular redundancy), errors can be
automatically corrected through majority voting.
Regarding the final project, students may form groups of 1 to 3
members (the project’s difficulty will depend on the group size and
members’ backgrounds). Please refer to last year’s projects for
reference and send an email to jserv.tw@gmail.com,
specifying your group members and proposed project topics (you may
suggest multiple topics, with the final decision made by the
instructor).
