版本 56b9e07020db2a57422e5894ee154cb0298f58ec

Computer Architecture

Instructor: Jim Huang (黃敬群) <jserv.tw@gmail.com>
Facebook Group: https://www.facebook.com/groups/system.software2022/
Policy
- Follow the classes: CS 61C at UC Berkeley, CS152/252: Computer Architecture
Course grading
- Quiz (30%), Homework (30%), Final/Term Project (40%)
Schedule is tentative and subject to change!

Computer Architecture (Fall 2022)

Week 1 (Sep 6): Introduction / Online via YouTube
- Course Introduction
- David Patterson: A New Golden Age for Computer Architecture: History, Challenges and Opportunities / video
  - Article, note
- David Patterson: From Mainframe CPUs to Neural-Network TPUs and Open RISC-V / video
- Great Ideas in Computer Architecture, Intro / video
- Number Representation / video
- Floating Point / video
- C Memory Management / video
Week 2 (Sep 13): Quiz + RISC-V / Online via YouTube
- Quiz1: C programming, bit-wise operations, number representation, floating-point / Solution
- Lab0: Web-based Emulators
- RISC-V Instructions
  - The RISC-V Instruction Set Manual: Volume I: Unprivileged ISA
- Intro to Assembly Language and RISC-V / video
Week 3 (Sep 20): RISC-V / Online via YouTube
- Intro to Assembly Language and RISC-V / video
  - RISC-V Assembly Programmer’s Manual
- RISC-V Data Transfer / video
- RISC-V Decision Making
- Functions Calls with RISC-V / video
- Lab1: RV32I Simulator
- Assignment: Homework1: RISC-V Assembly and Instruction Pipeline (Due: Oct 10, 2022)
Week 4 (Sep 27): RISC-V / Online via YouTube
- Announcement:
  - Next quiz is scheduled to Oct 4
  - Code Review for Homework 1 on Oct 4
- NASA, Microchip, SiFive Announces Partnership for RISC-V Spaceflight Computing Platform
- ST, CAES team on octacore RISC-V space chip with selectable cores
- Apple M1 Pro/Max
  - ARM1 (1985) vs. Apple M1 Max (2021)
  - Apple Announces M1 Pro & M1 Max: Giant New Arm SoCs with All-Out Performance / Apple M2
- Calling Convention for RISC-V / video
- CALL = Compiling, Assembling, Linking, and Loading / video
- 2021-Quiz2 / solution
Week 5 (Oct 4): Quiz + Code Review (Room 4201 (1F) at (old) CSIE Building)
- Quiz2: RISC-V assembly and C programming / solution
- Code Review on Homework1: RISC-V Assembly and Instruction Pipeline
Week 6 (Oct 11): RISC-V Instruction Format + GNU Toolchain / Online via YouTube
- Next week: digital logic
- Further reading FPGA design for Software Engineers
- Lab2: RISC-V RV32I[MACF] emulator with ELF support
- Assignment: Homework2: RISC-V Toolchain (Due: Oct 31)
- RISC-V Instruction Formats Part I / Part II / video
Week 7 (Oct 18): Digital Systems / Online via YouTube
- Announcement: New quiz is scheduled on Oct 25
- Binary marble adding machine / video
  - Yes, you can implement a few logic-like elements without electricity.
  - Logic gates are primarily implemented using diodes or transistors acting as electronic switches, but can also be constructed using vacuum tubes, electromagnetic relays (relay logic), fluidic logic, pneumatic logic, optics, molecules, or even mechanical elements. Now, most logic gates are made from MOSFETs (metal–oxide–semiconductor field-effect transistors).
- nand2tetris
- Synchronous Digital Systems (SDS), Boolean Algebra / video
  - sequential logic is a type of logic circuit whose output depends on the present value of its input signals and on the sequence of past inputs, the input history.
- State, Combinational Logic / video
- 2020-Quiz3 / solution
- 2021-Quiz3 / solution
Week 8 (Oct 25): Datapath and Control
- Quiz3: RISC-V programming and instruction encoding + Digital systems / solution
- RISC-V CPU Datapath, Control Intro / video
- Single-Cycle CPU Control / video
Week 9 (Nov 1): Pipeline
- Announcement:
  - Next quiz is scheduled to Dec 7
- Quiz4: Digital systems / solution
- video: Are Computers Still Getting Faster?
- MIT 6.004 L15: Introduction to Pipelining, L16: Processor Pipelining, L17: Implementing Pipelining
  - slides: Introduction to Pipelining
  - slides: Pipelined Processors
  - note
Week 10 (Nov 8): Pipelined Processors
- Announcement:
  - Next quiz is scheduled to Dec 7
  - Homework3: SoftCPU is out.
  - Next week, we will review all the assignments.
- 0 to ASIC
- L16: Processor Pipelining, L17: Implementing Pipelining, L18: Implementing Pipelined Processors / note
  - slides: Pipelined Processors
  - slides: Pipelined Processors Data and Control Hazards
- RISC-V 5-Stage Pipeline / Hazards / video
- Complex Pipelines, Out-of-Order Issue, Register Renaming
- Lab3: srv32 - RISCV RV32IM Soft CPU
- Assignment: Homework3: SoftCPU (Due: Dec 20, 2021)
- 2020 Quiz4
  - solution
Week 11 (Nov 8): Quiz + Homework Review
- Quiz5: RISC-V programming + datapath + control + pipelined processor / solution
- Homework1, Homework2
Week 12 (Nov 15): Cache + Virtual Memory
- Announcement: Quiz on Dec 21 - pipeline, cache and virtual memory
- Caches: Direct-mapped, set-associative / video
- Multi-level Caches, Cache Questions / video
- The golden age of ever-changing computer architecture
  - Cerebras announced a system which connects multiple integrated circuits (commonly called “chips”) into a neural network with many connections in Aug 2021. It enables a single system to support AI models with more than 120 trillion parameters.
- Virtual Memory / video
  - UCB: Virtual Memory / video
- 2020-Quiz5 / solution
Week13 (Nov 22): Quiz + Virtual Memory + Operating System
- Announcement:
  - Be aware of term projects.
  - Next week, we will review all the assignments.
- Quiz6: pipelined processor + cache + virtual memory / solution
- Virtual Memory / video
- Lab4: Cache
  - Reference work
- Operating Systems / video
- Term projects 2020
Week14 (Nov 29): Synchronization
- Announcement:
  - Quiz on Jan 11
  - Your grades will be delivered on Jan 21, 2022
  - Check the listing of final/term projects
- Term projects 2021
- Synchronization / video
- Thread-Level Parallelism / video
  - Let’s skip OpenMP part
Week15 (Dec 6): Operating System and RISC-V, cache coherence
- Announcement:
  - Quiz7 on Jan 11
  - Check the listing of final/term projects
- video: The Future of Operating Systems on RISC-V / transcript
- Multithreading Issues, Cache Coherency / video
  - Let’s skip OpenMP part
- Freestanding RISC-V Programs
  - bare metal
- Multithreaded Application Synchronization Part I
  - Taken from CSCI 463: Computer Architecture and Systems Organization
  - RISC-V spec references the word ‘hart’ - what does ‘hart’ mean?
- Multithreaded Application Synchronization Part II
  - RISC-V AMOSWAP instruction
- Advanced topics on Synchronization - 1
- Advanced topics on Synchronization - 2
- 2020 Quiz6
  - solution
Week16 (Dec 13): I/O
- Quiz7 / solution
- I/O: Devices, Polling, Interrupts / video
  - Traps/Interrupts/Exceptions
  - Trap Handling in 5-Stage Pipeline
Week17 (Dec 20): Modern Processors
Week 18 (Dec 27): Modern Processors