版本 6f4bfd6f776bba0e1fd30cfdfb8a8af99dbbacfb
Computer Architecture
- Instructor: Jim Huang (黃敬群)
<jserv.tw@gmail.com> - Facebook Group: https://www.facebook.com/groups/system.software2021/
- Policy
- Follow the classes: CS 61C at UC Berkeley, CS152/252: Computer Architecture
- Course grading
- Quiz (20%), Homework (40%), Final Project (40%)
- Schedule is tentative and subject to change!
Computer Architecture (Fall 2021)
- Week 1 (Sep 28): Introduction
- Course Introduction
- David Patterson: A New Golden Age for Computer Architecture: History, Challenges and Opportunities / video
- David Patterson: From Mainframe CPUs to Neural-Network TPUs and Open RISC-V / video
- Great Ideas in Computer Architecture, Intro / video
- Number Representation
- Floating Point
- C Memory Management / video
- Week 2 (Oct 5): Quiz + RISC-V
- Quiz1: C programming, bit-wise operations, number representation, floating-point / Solution
- Lab0: Web-based Emulators
- Introduction to RISC-V Assembly language : Arithmetic
- Intro to Assembly Language and RISC-V / video
- Week 3 (Oct 12): RISC-V
- Week 4 (Oct 19): RISC-V
- Announcement:
- Next quiz is scheduled to Oct 26
- Code Review for Homework 1 on Oct 26
- We might be in a physical classroom next week. Please check the latest announcement via email.
- Apple M1 Pro/Max
- More RISC-V Functions / video
- Compiler, Assembler, Linker, Loader / video
- 2020-Quiz2
- Announcement:
- Week 5 (Oct 26): Quiz + Code Review (Room 4201 (1F) at (old) CSIE Building)
- Quiz2: RISC-V assembly and C programming / solution
- Code Review on Homework1: RISC-V Assembly and Instruction Pipeline
- Week 6 (Nov 2): RISC-V Instruction Format + GNU Toolchain + Code Review (Room 4201 (1F) at (old) CSIE Building)
- Next week: digital logic
- Code Review on Homework1: RISC-V Assembly and Instruction Pipeline
- Lab2: RISC-V RV32I[MA] emulator with ELF support
- Assignment: Homework2: RISC-V Toolchain (Due: Nov 15)
- Further reading FPGA design for Software Engineers
- RISC-V Instruction Formats / video
- Week 7 (Nov 9): Digital Systems
- Announcement: New quiz on Nov 16
- Next generation of rv32emu: sysprog21/rv32emu-next
- Combinational Digital Logic / video
- Sequential Digital Logic / video
- 2020-Quiz3
- Week 8 (Nov 16): Datapath and Control
- Announcement: Due to internal problems of HackMD (pictures were not shown), we would take new scoring method to eliminate the impact. Next week, we have an additional quiz dedicated to Combinational and Sequential Digital Logic.
- Quiz3: RISC-V programming and instruction encoding + Digital systems / solution
- RISC-V CPU Datapath, Control Intro / video
- Single-Cycle CPU Control / video
- Week 9 (Nov 23): Pipeline
- Announcement:
- Next quiz is scheduled to Dec 7
- Quiz4: Digital systems / solution
- video: Are Computers Still Getting Faster?
- MIT 6.004 L15: Introduction to Pipelining, L16: Processor Pipelining, L17: Implementing Pipelining / note
- Announcement:
- Week 10 (Nov 30): Pipelined Processors
- Announcement:
- Next quiz is scheduled to Dec 7
- Homework3: SoftCPU](2020-arch-homework3) is out
- 0 to ASIC
- RISC-V: Why the ISA battles are not over yet
- L18: Implementing Pipelined Processors
- RISC-V 5-Stage Pipeline / Hazards / video
- Complex Pipelines, Out-of-Order Issue, Register Renaming
- srv32 - RISCV RV32IM Soft CPU
- Assignment: Homework3: SoftCPU (Due: Dec 13, 2021)
- 2020 Quiz4
- Announcement:
- Week 11 (Dec 7): Quiz + Homework Review
- Quiz5: RISC-V programming + datapath + control + pipelined processor / solution
- 13-Year-Old, Nicholas Sharkey, Creates a RISC-V Core
- ARM1 vs. Apple M1
- Week 12 (Dec 14): Cache + Virtual Memory
- Announcement: Quiz on Dec 1 - pipeline, cache and virtual memory
- Caches: Direct-mapped, set-associative / video
- Multi-level Caches, Cache Questions / video
- The golden age of ever-changing computer architecture
- Virtual Memory / video
- Week13 (Dec 21): Quiz + Virtual Memory
- Quiz5
- Virtual Memory / video
- Term projects 2019
- Implement RISC-V Compressed Instruction Set on rv32emu
- Implement RISC-V Compressed Instruction Set for Reindeer, based on pull request RV32C support. must be validated on Step CYC10 FPGA board.
- Contribute to Ripes: pick up pending issues, work on them, and finally send pull request(s).
- Prepare practical tutorials for VSRTL, thus people can follow the instructions for implementing minimal RISC-V core such as minrv32.
- Analyze spu32 with Yosys open synthesis suite. Explain how it works and validate it.
- Analyze VexRiscv. Explain how it works and validate it.
- Modify Reindeer to allow non-trial interactive games on Step CYC10 FPGA board, based on Reindeer_Step and Zephyr RTOS.
- Lab4: Cache
- Week14 (Dec 28): Synchronization
- Announcement: Quiz on Dec 22
- Assignment: Homework4: Cache (Due: ?)
- Operating Systems / video
- Synchronization / video
- Thread-Level Parallelism / video
- Week15 (Jan 4): Operating System and RISC-V
- Week16 (Jan 11): I/O, cache coherence
- Term projects 2020
- Quiz6
- I/O: Devices, Polling, Interrupts / video
- Traps/Interrupts/Exceptions
- Trap Handling in 5-Stage Pipeline
- Multithreading Issues, Cache Coherency / video
- Cache Coherence / video
- Modern microprocessors usually have 2 to 8 cores where each core has a private cache for performance
- Modified/Shared/Invalid (MSI) Protocol, MESI: An Enhanced MSI protocol to increased performance for private read-write data
- Week17 (Jan 18): Modern Processors
