版本 c97ead2761b8a4504d64903379d0b37a08ec549e
Computer Architecture
- Instructor: Jim Huang (黃敬群)
<jserv.tw@gmail.com> - Facebook Group: https://www.facebook.com/groups/system.software2025/
- Policy
- Follow the classes: CS 61C at UC Berkeley, CMU 18-447: Introduction to Computer Architecture
- Course grading
- Quiz (30%), Homework (30%), Final/Term Project (40%)
- NOTICE: You must participate in at least one post-quiz or homework oral discussion in person before December 30, 2025; otherwise, no credit will be awarded for quizzes.
- Guidelines for Student Use of AI Tools
- Schedule is tentative and subject to change!
Computer Architecture (Fall 2025)
- Week 1 (Sep 9): Introduction
- Announcement
- There will be a quiz next week. After the quiz, we will begin oral discussions, and you are expected to attend them in person.
- Course Introduction
- David Patterson: A New Golden Age for Computer Architecture: History, Challenges and Opportunities / video / note
- David Patterson: From Mainframe CPUs to Neural-Network TPUs and Open RISC-V / video
- Great Ideas in Computer Architecture / video
- Number Representation / video
- Understanding Floating Point Struggles / Floating Point (video)
- C Memory Management / video
- Announcement
- Week 2 (Sep 16): Quiz
- Quiz1: C programming, bit-wise operations, number representation, floating-point / Solutions
- Follow-ups: Approximating sine function, Square Root, callback function, bfloat16
- Principles of this course
- Intro to RISC-V / video
- RISC-V Instructions
- Week 3 (Sep 23): RISC-V
- Announcement:
- Guidelines for Student Use of AI Tools
- Quiz2 is scheduled on Sep 30.
- 2024 Quiz2: RISC-V assembly and C programming / solution
- 2023 Quiz2: RISC-V assembly and C programming / solution
- 2022 Quiz2: RISC-V assembly and C programming / solution
- 2021 Quiz2: RISC-V assembly and C programming / solution
- Homework 1 is out.
- Code Review for Homework 1 on Oct 7
- If you voluntarily participate in the class discussions for Quiz1, please email the instructor afterward, including your responses to the instructor’s questions and any follow-up contributions. You will receive an additional 10 points for Quiz 1.
- RISC-V Data Transfer / video
- RISC-V Decision Making and Logical Operations / video
- RISC-V Procedures / video
- Lab0: Web-based Emulators
- Lab1: RV32I Assembly
- Assignment: Homework1: RISC-V Assembly and Instruction Pipeline (Due: Oct 13, 2025)
- Announcement:
- Week 4 (Sep 30): Quiz + RISC-V
- Announcement
- Code Review on Homework1: RISC-V Assembly and Instruction Pipeline next week
- Quiz2:
RISC-V assembly and C programming / solution
- Follow-ups: LED matrix, Tower of Hanoi
- Recursion as a Problem-Solving Technique
- Fixed-point Arithmetic
- RISC-V Instruction Formats Part I / video
- RISC-V Instruction Formats Part II / video
- Announcement
- Week 5 (Oct 7): RV32I + Code Review
- Announcement
- In today’s class, we will discuss the progress of Homework 1 with the students. Whether you are voluntarily or non-voluntarily participating in the Q&A, you should follow the assignment guidelines, prepare your HackMD notes, and set them to public. When the instructor talks with you, you should paste the link to your HackMD notes for Homework 1 here. \(\to\) 2025-10-07
- Quiz 3 is scheduled for Oct 21. Be sure to carefully review past quizzes, understand their level of difficulty, and practice thoroughly.
- Review: RISC-V Architecture
Instruction Encoding
- Revisit the RV32I specification and instruction encoding, as they serve as the foundation for implementing RISC-V processor cores in HDL.
- The system instructions:
ecall,ebreak, andcsr*. - online tool for RISC-V Instruction Encoder/Decoder / source code
- Code Review on Homework1: RISC-V Assembly and Instruction Pipeline
- Announcement
- Week 6 (Oct 14): Toolchain + Digital Systems
- Announcement
- Quiz 3 is scheduled for Oct 21 and will cover RISC-V assembly programming, software optimizations, instruction encoding, sequential logic, and combinational logic.
- The follow-ups for Quizzes 1 and 2, including lecture discussions and further improvements, have been updated in the syllabus. Please review them carefully.
- Homework 2 will be assigned next week, focusing on bare-metal programming, an essential skill for embedded system engineers. Search bare-metal via Google Career.
- Compiling, Assembling, Linking, and Loading / video-1 + video-2
- Freestanding RISC-V Programs
- Lab2: RISC-V for RV32I bare-metal programming
- Revisit Quiz
1
- World’s Fastest Square Root: Newton’s Method (The subject line is somewhat misleading; we can improve it further.)
- Binary marble adding
machine / video
- Yes, you can implement a few logic-like elements without electricity.
- Logic gates are primarily implemented using diodes or transistors acting as electronic switches, but can also be constructed using vacuum tubes, electromagnetic relays (relay logic), fluidic logic, pneumatic logic, optics, molecules, or even mechanical elements. Now, most logic gates are made from MOSFETs (metal–oxide–semiconductor field-effect transistors).
- Synchronous Digital Systems (SDS) / video
- Combinational
Logic / video
- sequential logic is a type of logic circuit whose output depends on the present value of its input signals and on the sequence of past inputs, the input history.
- SDS State / video
- Combinational Logic Blocks / video
- Announcement
- Week 7 (Oct 21): Quiz
- Announcement:
- Homework 2 is out. Deadline: Nov 12, 2025
- Quiz3: RISC-V programming and instruction encoding + Digital systems / solution
- Announcement:
- Week 8 (Oct 28): Review + Datapath and Control
- “What I cannot create, I do not understand.” - On Richard Feynman’s blackboard at the time of his death in 1988 / Build Your Own X
- RISC-V Datapath I / video
- Week 9 (Nov 4): Datapath and Control + Pipeline
- video: Are Computers Still Getting Faster?
- video: Circuits recap
- RISC-V Datapath II / video
- RISC-V Processor Design Control / video
- Constructing Hardware in a Scala Embedded Language (Chisel) is an
open-source hardware description language (HDL) used to describe digital
electronics and circuits at the register-transfer level that facilitates
advanced circuit generation and design reuse for both ASIC and FPGA
digital logic designs.
- slides
- Finite impulse response (FIR)
- Learn
Chisel online!
- Please run the cell blocks by either pressing SHIFT+ENTER on your keyboard
- MIT 6.191 L15: Introduction to Pipelining, L16: Processor Pipelining
- Week 10 (Nov 11): Pipelined Processors
- Announcement:
- Next week, we will continue reviewing all the assignments.
- Quiz 4 is scheduled next week.
- The next homework assignment will be given out next week, along with Quiz 4. Please review last year’s homework to get familiar with the procedure and expectations.
- rv32emu development, capable of running Linux kernel smoothly (#508)
- 0 to ASIC
- L16: Processor Pipelining, L17: Implementing Pipelining, L18: Implementing Pipelined Processors / note
- RISC-V 5-Stage Pipeline / video-1, video-2, video-3
- Lab3: Construct a single-cycle CPU with Chisel
- Announcement:
- Week 11 (Nov 18): Quiz + Homework Review
- Week 12 (Nov 25): Cache
- Week13 (Dec 2): Virtual Memory + Operating System + Vector Extension
- Announcement:
- Quiz 5 is scheduled on Dec 10
- This semester, we will conduct 7 quizzes. Out of these, the best 4 will be selected for grading purposes.
- The instructor will submit the grades on the school’s designated deadline (Jan 24, 2025) for grade registration. This means that students will have ample time to dedicate to the final project assigned in this course.
- Term projects will be listed on Dec 5. Term projects of 2023
- News: Intel Announces Retirement of CEO Pat Gelsinger - Early last month, Intel was removed from the Dow Jones Industrial Average, which comprises 30 leading U.S. stocks, to make room for Nvidia as the index shifts toward AI pioneers. / What Is the Dow Jones Industrial Average?
- Lab3: Construct a RISC-V CPU with Chisel
- Virtual Memory
- UCB: Virtual Memory I / video
- UCB: Virtual Memory II / video
- The Future of Mission
Critical Edge Compute Is RISC-V
- (12:47) multi-core flexibility: SMP, AMP, hypervisor
- Lockstep systems are fault-tolerant computers that simultaneously perform identical operations in parallel. Borrowed from military marching terminology, these systems use redundancy to detect and correct errors. With two systems (dual modular redundancy), errors can be identified, and with three systems (triple modular redundancy), errors can be automatically corrected through majority voting.
- Customizing Linux Systems in Aerospace
- UCB: Operating Systems
- RISC-V Vector extension (RVV)
- Announcement:
- Week14 (Dec 9): Quiz + Synchronization
- Announcement:
- Regarding the final project, students may form groups of 1 to 3
members (the project’s difficulty will depend on the group size and
members’ backgrounds). Please refer to last year’s projects for
reference and send an email to
jserv.tw@gmail.com, specifying your group members and proposed project topics (you may suggest multiple topics, with the final decision made by the instructor). - Check the listing of final/term projects in 2023 for reference.
- Regarding the final project, students may form groups of 1 to 3
members (the project’s difficulty will depend on the group size and
members’ backgrounds). Please refer to last year’s projects for
reference and send an email to
- Quiz5: pipelined processor + cache + virtual memory / solution
- Debunking CISC vs RISC code density
- Synchronization
- Please check your operating system textbook for such topic.
- Announcement:
- Week15 (Dec 16): Operating System, Multithreading
- Announcement:
- Quiz6 is scheduled on Dec 24
- Term Projects: You must provide the materials and demonstrate to the lecturer before Jan 23, 2025
- Synchronization
- Please check your operating system textbook for such topic.
- Multithreading
Issues + Cache Coherency
- Let’s skip OpenMP part
- video: The Future of Operating Systems on RISC-V / transcript
- Multithreaded Application
Synchronization Part I / Part
II
- Taken from CSCI 463: Computer Architecture and Systems Organization
- RISC-V AMOSWAP instruction
- RISC-V spec references the word ‘hart’ - what does ‘hart’ mean?
- Announcement:
- Week16 (Dec 23): Quiz + Memory Model, I/O
- Announcement:
- The class will be held online next week. (Happy New Year!) Please check this page for updates.
- Quiz7 is scheduled on Jan 7, 2025.
- The term projects will be reviewed on Jan 7.
- Quiz6 / solution
- Memory Model / slides
- I/O:
Devices, Polling, Interrupts / video
- Traps/Interrupts/Exceptions
- Trap Handling in 5-Stage Pipeline
- Announcement:
- Week17 (Dec 30): Modern Processors | online via YouTube start
at 09:15AM
- Announcements
- Quiz7 is scheduled on Jan 7, 2025
- Update term projects and contact the instructor if you didn’t receive the confirmation letter
- Modern Processor Architecture
- Introduction to Dynamic Branch Prediction, Advanced Branch Prediction
- Tournament Predictors and Branch Prediction Accuracy
- Project: Analyze and improve srv32
- Hardware Based Speculation
- RISC vs. CISC by John Mashey, one of the founders of the Standard Performance Evaluation Corporation (SPEC) benchmarking group.
- Announcements
- Week 18 (Jan 6): Review
- Quiz7 / solution
- Review term projects
