NOTICE: You must participate in at least one post-quiz or homework
oral discussion in person before December 30, 2025; otherwise, no credit
will be awarded for quizzes.
Schedule is tentative and subject to change!
Computer Architecture (Fall
2025)
Week 1 (Sep 9): Introduction
Announcement
There will be a quiz next week. After the quiz, we will begin oral
discussions, and you are expected to attend them in person.
Quiz2 is scheduled on Oct 1: Due to the possibility that the
classroom capacity may not accommodate the number of enrolled students,
additional classrooms may be arranged as test venues. Please make sure
to check this page on the evening of September 30th for related
announcements.
Due to the impact of Typhoon Krathon, Quiz 2 will be conducted
online instead of in-person. Please refresh this web page to obtain the
latest information on how to participate in the online quiz and attend
the course remotely.
Access the live-streamed course on YouTube. Watch the live
stream carefully: Quiz 2 participation instructions will be provided
during the broadcast.
Quiz 3 is scheduled for Oct 22 and will cover RISC-V assembly
programming, software optimizations, instruction encoding, sequential
logic, and combinational logic.
Yes, you can implement a few logic-like elements without
electricity.
Logic gates are primarily implemented using diodes or transistors
acting as electronic switches, but can also be constructed using vacuum
tubes, electromagnetic relays (relay logic), fluidic logic, pneumatic
logic, optics, molecules, or even mechanical elements. Now, most logic
gates are made from MOSFETs (metal–oxide–semiconductor field-effect
transistors).
sequential logic is a type of logic circuit whose output depends on
the present value of its input signals and on the sequence of past
inputs, the input history.
Constructing Hardware in a Scala Embedded Language (Chisel) is an
open-source hardware description language (HDL) used to describe digital
electronics and circuits at the register-transfer level that facilitates
advanced circuit generation and design reuse for both ASIC and FPGA
digital logic designs.
The next homework assignment will be given out next week, along with
Quiz 4. Please review last year’s
homework to get familiar with the procedure and expectations.
This semester, we will conduct 7 quizzes. Out of these, the best 4
will be selected for grading purposes.
The instructor will submit the grades on the school’s designated
deadline (Jan 24,
2025) for grade registration. This means that students will have
ample time to dedicate to the final project assigned in this
course.
Lockstep
systems are fault-tolerant computers that simultaneously perform
identical operations in parallel. Borrowed from military marching
terminology, these systems use redundancy to detect and correct errors.
With two systems (dual modular redundancy), errors can be identified,
and with three systems (triple modular redundancy), errors can be
automatically corrected through majority voting.
Regarding the final project, students may form groups of 1 to 3
members (the project’s difficulty will depend on the group size and
members’ backgrounds). Please refer to last year’s projects for
reference and send an email to jserv.tw@gmail.com,
specifying your group members and proposed project topics (you may
suggest multiple topics, with the final decision made by the
instructor).
