版本 f32a6ce4c6cd1bfc61865f8866239f3231708297
Computer Architecture
- Instructor: Jim Huang (黃敬群)
<jserv.tw@gmail.com> - Facebook Group: https://www.facebook.com/groups/system.software2022/
- Policy
- Follow the classes: CS 61C at UC Berkeley, CS152/252: Computer Architecture
- Course grading
- Quiz (30%), Homework (30%), Final/Term Project (40%)
- Schedule is tentative and subject to change!
Computer Architecture (Fall 2023)
- Week 1 (Sep 5): Introduction
- Course Introduction
- David Patterson: A New Golden Age for Computer Architecture: History, Challenges and Opportunities / video
- David Patterson: From Mainframe CPUs to Neural-Network TPUs and Open RISC-V / video
- Great Ideas in Computer Architecture, Intro / video
- Number Representation / video
- Floating Point / video
- C Memory Management / video
- Week 2 (Sep 12): Quiz + RISC-V
- Quiz1: C programming, bit-wise operations, number representation, floating-point / Solution
- Lab0: Web-based Emulators
- RISC-V Instructions
- Intro to Assembly Language and RISC-V / video
- Week 3 (Sep 19): RISC-V
- Week 4 (Sep 26): RISC-V
- Announcement:
- Next quiz is scheduled to Oct 4
- Code Review for Homework 1 on Oct 4
- NASA, Microchip, SiFive Announces Partnership for RISC-V Spaceflight Computing Platform
- ST, CAES team on octacore RISC-V space chip with selectable cores
- Apple M1 Pro/Max
- Calling Convention for RISC-V / video
- CALL = Compiling, Assembling, Linking, and Loading / video
- 2021-Quiz2 / solution
- Announcement:
- Week 5 (Oct 3): Quiz + Code Review (Room 4201 (1F) at (old) CSIE Building)
- Quiz2: RISC-V assembly and C programming / solution
- Code Review on Homework1: RISC-V Assembly and Instruction Pipeline
- Week 6 (Oct 10): RISC-V Instruction Format + GNU Toolchain
- Next week: digital logic
- Further reading FPGA design for Software Engineers
- Lab2: RISC-V RV32I[MACF] emulator with ELF support
- Assignment: Homework2: RISC-V Toolchain (Due: Oct 31)
- RISC-V Instruction Formats Part I / Part II / video
- Week 7 (Oct 17): Digital Systems
- Announcement: New quiz is scheduled on Oct 25
- Binary marble adding machine / video
- Yes, you can implement a few logic-like elements without electricity.
- Logic gates are primarily implemented using diodes or transistors acting as electronic switches, but can also be constructed using vacuum tubes, electromagnetic relays (relay logic), fluidic logic, pneumatic logic, optics, molecules, or even mechanical elements. Now, most logic gates are made from MOSFETs (metal–oxide–semiconductor field-effect transistors).
- nand2tetris
- Synchronous Digital Systems (SDS), Boolean Algebra / video
- sequential logic is a type of logic circuit whose output depends on the present value of its input signals and on the sequence of past inputs, the input history.
- State, Combinational Logic / video
- 2020-Quiz3 / solution
- 2021-Quiz3 / solution
- 2021-Quiz4 / solution
- Week 8 (Oct 24): Datapath and Control + Code Review (Room 4201 (1F) at (old) CSIE Building)
- Quiz3: RISC-V programming and instruction encoding + Digital systems / solution
- RISC-V CPU Datapath / video
- Week 9 (Oct 31): Pipeline
- Week 10 (Nov 7): Pipelined Processors
- Announcement:
- The next quiz is planned on Nov 15.
- Homework3 SoftCPU is out.
- Next week, we will review all the assignments.
- Recent rv32emu changes
- More descriptions about system calls. See docs/syscall.md
- Implement
clock_gettimesystem call, so that you can callgettimeofday/clock_gettimein C programs. - Implement user-level counters for getting CPU cycle counts in RISC-V programs. See tests/perfcounter for sample usage.
- Better experiences while running Doom and Quake games. You can resize the window and use mouse properly.
- More test programs: jit-bf (JIT assembler for RISC-V), coro (a simple coroutine implementation for RISC-V), mandelbrot (an ASCII-based renderer for Mandelbrot Set, colorized), richards (an operating system task scheduler simulation benchmark), and chacha20 (stream cipher)
- More comments in source files.
- 0 to ASIC
- L16: Processor Pipelining, L17: Implementing Pipelining, L18: Implementing Pipelined Processors / note
- RISC-V 5-Stage Pipeline / Hazards / video
- Lab3: srv32 - RISCV RV32IM Soft CPU
- Assignment: Homework3: SoftCPU (Due: Nov 30, 2022)
- 2020 Quiz4 / solution
- 2021 Quiz5 / solution / annotated with Ripes
- Announcement:
- Week 11 (Nov 14): Quiz + Homework Review (Room 4201 (1F) at (old) CSIE Building)
- Quiz4: RISC-V programming + datapath + control + pipelined processor / solution
- Homework1, Homework2
- Complex Pipelines, Out-of-Order Issue, Register Renaming
- Week 12 (Nov 21): Cache + Virtual Memory
- Announcement
- Quiz on Nov 29 - pipeline, cache and virtual memory (partial)
- Term projects will be listed on Nov 29
- Caches: Direct-mapped, set-associative / video
- Multi-level Caches, Cache Questions / video
- The golden age of ever-changing computer architecture
- Virtual Memory / UCB: Virtual Memory / video
- 2021-Qui6 / solution / with Ripes simulation
- 2020-Quiz5 / solution
- Announcement
- Week13 (Nov 28): Quiz + Virtual Memory + Operating System (Room 4201 (1F) at (old) CSIE Building)
- Announcement:
- Be aware of Term projects
- Quiz5: pipelined processor + cache + virtual memory / solution
- Virtual Memory / video
- Lab4: Cache
- Operating Systems / video
- Announcement:
- Week14 (Dec 5): Synchronization
- Announcement:
- Quiz6 on Dec 13
- Check the listing of final/term projects and fill in your names.
- Apple Silicon Guide
- Debunking CISC vs RISC code density
- Operating Systems / video
- Synchronization
- Please check your operating system textbook for such topic.
- Thread-Level Parallelism / video
- Let’s skip OpenMP part
- Multithreading Issues + Cache Coherency / video
- 2021 Quiz7 /solution
- 2021 Quiz6 /solution
- 2020 Quiz6 /solution
- Announcement:
- Week15 (Dec 12): suspended
- Announcement:
- Quiz6 will be postponed to Dec 20
- Quiz7 on Dec 27
- Check the listing of final/term projects
- Announcement:
- Week16 (Dec 19): Multithreading, Synchronization, I/O
- Quiz6 / solution
- video: The Future of Operating Systems on RISC-V / transcript
- Freestanding RISC-V Programs
- Multithreaded Application Synchronization Part I
- Multithreaded Application Synchronization Part II
- RISC-V AMOSWAP instruction
- Advanced topics on Synchronization - 1
- Advanced topics on Synchronization - 2
- I/O: Devices, Polling, Interrupts / video
- Traps/Interrupts/Exceptions
- Trap Handling in 5-Stage Pipeline
- Week17 (Dec 26): Modern Processors
- Quiz7 / solution
- listing of final/term projects
- You must provide the materials and demonstrate to the lecturer before Jan 13, 2023.
- Summarize what you did and send email to
<jserv.tw@gmail.com>.
- Modern Processor Architecture
- Introduction to Dynamic Branch Prediction, Advanced Branch Prediction, Tournament Predictors and Branch Prediction Accuracy
- Project: Analyze and improve srv32
- Hardware Based Speculation
- Week 18 (Jan 2): Modern Processors
- Modern Processor Architecture
- Introduction to Dynamic Branch Prediction, Advanced Branch Prediction, Tournament Predictors and Branch Prediction Accuracy
- Project: Analyze and improve srv32
- Hardware Based Speculation
- Case study: VRoom - very high end RISC-V implementation, cloud server class, out of order, super scalar, speculative, up to 8 IPC
- RISC vs. CISC by John Mashey, one of the founders of the Standard Performance Evaluation Corporation (SPEC) benchmarking group.
