Introduction

General Purpose Input/Output (GPIO) is a generic pin on a chip whose behavior (including whether it is an input or output pin) can be controlled (programmed) by the user at run time.

In STM32F4-Discovery, each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR), a 32-bit set/reset register (GPIOx_BSRR), a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection register (GPIOx_AFRH and GPIOx_AFRL).

Main Feature

• Up to 16 I/Os under control
• Output states: push-pull or open drain + pull-up/down
• Output data from output data register (GPIOx_ODR) or peripheral (alternate function output)
• Speed selection for each I/O
• Input states: floating, pull-up/down, analog
• Input data to input data register (GPIOx_IDR) or peripheral (alternate function input)
• Bit set and reset register (GPIOx_BSRR) for bitwise write access to GPIOx_ODR
• Locking mechanism (GPIOx_LCKR) provided to freeze the I/O configuration
• Analog function
• Alternate function input/output selection registers (at most 16 AFs per I/O)
• Fast toggle capable of changing every two clock cycles
• Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several peripheral functions

Functional Description

Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in several modes:

• Input floating
• Input pull-up
• Input-pull-down
• Analog
• Output open-drain with pull-up or pull-down capability
• Output push-pull with pull-up or pull-down capability
• Alternate function push-pull with pull-up or pull-down capability
• Alternate function open-drain with pull-up or pull-down capability

Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR register is to allow atomic read/modify accesses to any of the GPIO registers. In this way, there is no risk of an IRQ occurring between the read and the modify access.

Figure below shows the basic structure of a 5 V tolerant I/O port bit:

.. image:: /embedded/GPIO_basic_src.PNG

Configuration

Input configuration

When the I/O port is programmed as Input:

• the output buffer is disabled
• the Schmitt trigger input is activated
• the pull-up and pull-down resistors are activated depending on the value in the GPIOx_PUPDR register
• The data present on the I/O pin are sampled into the input data register every AHB1 clock cycle
• A read access to the input data register provides the I/O State

Output configuration

When the I/O port is programmed as output:

• The output buffer is enabled:
  • Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register leaves the port in Hi-Z (the P-MOS is never activated)
  • Push-pull mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register activates the P-MOS
• The Schmitt trigger input is activated
• The weak pull-up and pull-down resistors are activated or not depending on the value in the GPIOx_PUPDR register
• The data present on the I/O pin are sampled into the input data register every AHB1 clock cycle
• A read access to the input data register gets the I/O state
• A read access to the output data register gets the last written value

Alternate function configuration

When the I/O port is programmed as alternate function:

• The output buffer can be configured as open-drain or push-pull
• The output buffer is driven by the signal coming from the peripheral (transmitter enable and data)
• The Schmitt trigger input is activated
• The weak pull-up and pull-down resistors are activated or not depending on the value in the GPIOx_PUPDR register
• The data present on the I/O pin are sampled into the input data register every AHB1 clock cycle
• A read access to the input data register gets the I/O state

Supplement：

GPIOx_AFRL[31:0] and GPIOx_ARHL[31:0] provide ways to select alternation functions. However, different alternate functions maps to different bits of ports. Table below is part of alternate function mapping, which is mainly about USART2/3.

For more information, please refer to Table 8. Alternate function mapping from P.58-62 in STM32F407xx Datasheet.

.. image:: /embedded/af_mapping.png

Analog configuration

When the I/O port is programmed as analog configuration:

• The output buffer is disabled
• The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0).
• The weak pull-up and pull-down resistors are disabled
• Read access to the input data register gets the value “0”

Note: In the analog configuration, the I/O pins cannot be 5 Volt tolerant.

Demo

Reference

• General Purpose Input/Output - Wikipedia, the free encyclopedia <http://en.wikipedia.org/wiki/General_Purpose_Input/Output>_
• STM32F407xx Datasheet<http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATASHEET/DM00037051.pdf>_
• STM32F407xx Reference Manual<http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/REFERENCE_MANUAL/DM00031020.pdf>_
• 稀里糊塗學 STM32 第二講：源源不絕</embedded/learn-stm32-part-2.pdf>_
• GPIO PPT</embedded/GPIO_v3.ppt>_